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      1 ; RUN: llc -march=hexagon < %s | FileCheck %s
      2 
      3 target triple = "hexagon-unknown--elf"
      4 
      5 ; Check that we can predicate base+offset vector stores.
      6 ; CHECK-LABEL: sammy
      7 ; CHECK: if{{.*}}vmem(r{{[0-9]+}}+#0) =
      8 define void @sammy(<16 x i32>* nocapture %p, <16 x i32>* nocapture readonly %q, i32 %n) #0 {
      9 entry:
     10   %0 = load <16 x i32>, <16 x i32>* %q, align 64
     11   %sub = add nsw i32 %n, -1
     12   br label %for.body
     13 
     14 for.body:                                         ; preds = %if.end, %entry
     15   %p.addr.011 = phi <16 x i32>* [ %p, %entry ], [ %incdec.ptr, %if.end ]
     16   %i.010 = phi i32 [ 0, %entry ], [ %add, %if.end ]
     17   %mul = mul nsw i32 %i.010, %sub
     18   %add = add nuw nsw i32 %i.010, 1
     19   %mul1 = mul nsw i32 %add, %n
     20   %cmp2 = icmp slt i32 %mul, %mul1
     21   br i1 %cmp2, label %if.then, label %if.end
     22 
     23 if.then:                                          ; preds = %for.body
     24   store <16 x i32> %0, <16 x i32>* %p.addr.011, align 64
     25   br label %if.end
     26 
     27 if.end:                                           ; preds = %if.then, %for.body
     28   %incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.011, i32 1
     29   %exitcond = icmp eq i32 %add, 100
     30   br i1 %exitcond, label %for.end, label %for.body
     31 
     32 for.end:                                          ; preds = %if.end
     33   ret void
     34 }
     35 
     36 ; Check that we can predicate post-increment vector stores.
     37 ; CHECK-LABEL: danny
     38 ; CHECK: if{{.*}}vmem(r{{[0-9]+}}++#1) =
     39 define void @danny(<16 x i32>* nocapture %p, <16 x i32>* nocapture readonly %q, i32 %n) #0 {
     40 entry:
     41   %0 = load <16 x i32>, <16 x i32>* %q, align 64
     42   %sub = add nsw i32 %n, -1
     43   br label %for.body
     44 
     45 for.body:                                         ; preds = %if.end, %entry
     46   %p.addr.012 = phi <16 x i32>* [ %p, %entry ], [ %incdec.ptr3, %if.end ]
     47   %i.011 = phi i32 [ 0, %entry ], [ %add, %if.end ]
     48   %mul = mul nsw i32 %i.011, %sub
     49   %add = add nuw nsw i32 %i.011, 1
     50   %mul1 = mul nsw i32 %add, %n
     51   %cmp2 = icmp slt i32 %mul, %mul1
     52   br i1 %cmp2, label %if.then, label %if.end
     53 
     54 if.then:                                          ; preds = %for.body
     55   %incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.012, i32 1
     56   store <16 x i32> %0, <16 x i32>* %p.addr.012, align 64
     57   br label %if.end
     58 
     59 if.end:                                           ; preds = %if.then, %for.body
     60   %p.addr.1 = phi <16 x i32>* [ %incdec.ptr, %if.then ], [ %p.addr.012, %for.body ]
     61   %incdec.ptr3 = getelementptr inbounds <16 x i32>, <16 x i32>* %p.addr.1, i32 1
     62   %exitcond = icmp eq i32 %add, 100
     63   br i1 %exitcond, label %for.end, label %for.body
     64 
     65 for.end:                                          ; preds = %if.end
     66   ret void
     67 }
     68 
     69 attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
     70