1 ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s 2 ; Rely on the comments generated by llc. Check that "if.then" was predicated. 3 ; CHECK: while.body13 4 ; CHECK: if{{.*}}memd 5 ; CHECK: while.end 6 7 %struct.1 = type { i32, i32 } 8 %struct.2 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %struct.1], [5 x i32] } 9 10 @A1 = global i64 zeroinitializer 11 @A2 = global i64 zeroinitializer 12 @B1 = global i32 zeroinitializer 13 @B2 = global i32 zeroinitializer 14 @C1 = global i8 zeroinitializer 15 16 declare i32 @llvm.hexagon.S2.cl0(i32) nounwind readnone 17 declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) nounwind readnone 18 declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) nounwind readnone 19 declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) nounwind readnone 20 declare i64 @llvm.hexagon.A2.vaddws(i64, i64) nounwind readnone 21 declare i64 @llvm.hexagon.A2.vsubws(i64, i64) nounwind readnone 22 declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) nounwind readnone 23 24 define void @foo(i32 %n, i64* %ptr) #0 { 25 entry: 26 br label %while.body 27 28 while.body: 29 %count = phi i32 [ 0, %entry ], [ %next, %while.end ] 30 %idx = phi i32 [ 0, %entry ], [ %15, %while.end ] 31 %0 = load i32, i32* @B1, align 4 32 %1 = load i32, i32* @B2, align 8 33 %2 = and i32 %1, %0 34 br label %while.body13 35 36 while.body13: ; preds = %while.body, %if.end 37 %3 = phi i64 [ %13, %if.end ], [ 0, %while.body ] 38 %4 = phi i64 [ %14, %if.end ], [ 0, %while.body ] 39 %m = phi i32 [ %6, %if.end ], [ %2, %while.body ] 40 %5 = tail call i32 @llvm.hexagon.S2.cl0(i32 %m) 41 %6 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %m, i32 %5) 42 %cgep85 = getelementptr [10 x %struct.2], [10 x %struct.2]* inttoptr (i32 -121502345 to [10 x %struct.2]*), i32 0, i32 %idx 43 %cgep90 = getelementptr %struct.2, %struct.2* %cgep85, i32 0, i32 12, i32 %5 44 %7 = load i32, i32* %cgep90, align 4 45 %8 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %7, i32 %7) 46 %cgep91 = getelementptr %struct.2, %struct.2* %cgep85, i32 0, i32 13, i32 %5 47 %9 = load i32, i32* %cgep91, align 4 48 %10 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %8, i32 %9, i32 %9) 49 %11 = load i8, i8* @C1, align 1 50 %and24 = and i8 %11, 1 51 %cmp = icmp eq i8 %and24, 0 52 br i1 %cmp, label %if.then, label %if.end 53 54 if.then: ; preds = %while.body13 55 %12 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %3, i64 %10) 56 store i64 %12, i64* %ptr, align 8 57 br label %if.end 58 59 if.end: ; preds = %if.then, %while.body13 60 %13 = phi i64 [ %12, %if.then ], [ %3, %while.body13 ] 61 %14 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %4, i64 %10) 62 %tobool12 = icmp eq i32 %6, 0 63 br i1 %tobool12, label %while.end, label %while.body13 64 65 while.end: 66 %add40 = add i32 %idx, 1 67 %15 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %add40, i32 10) nounwind 68 %next = add i32 %count, 1 69 %cc = icmp eq i32 %next, %n 70 br i1 %cc, label %end, label %while.body 71 72 end: 73 store i64 %10, i64* @A2, align 8 74 ret void 75 } 76 77 attributes #0 = { nounwind "target-cpu"="hexagonv5" } 78
