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      1 ; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length64b < %s | FileCheck %s
      2 
      3 ; Test that we generate code for the vector byte enabled store intrinsics.
      4 
      5 ; CHECK-LABEL: f0:
      6 ; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
      7 
      8 define void @f0(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
      9 b0:
     10   %v0 = bitcast <16 x i32> %a0 to <512 x i1>
     11   tail call void @llvm.hexagon.V6.vS32b.qpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
     12   ret void
     13 }
     14 
     15 ; Function Attrs: argmemonly nounwind
     16 declare void @llvm.hexagon.V6.vS32b.qpred.ai(<512 x i1>, i8*, <16 x i32>) #0
     17 
     18 ; CHECK-LABEL: f1:
     19 ; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
     20 
     21 define void @f1(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
     22 b0:
     23   %v0 = bitcast <16 x i32> %a0 to <512 x i1>
     24   tail call void @llvm.hexagon.V6.vS32b.nqpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
     25   ret void
     26 }
     27 
     28 ; Function Attrs: argmemonly nounwind
     29 declare void @llvm.hexagon.V6.vS32b.nqpred.ai(<512 x i1>, i8*, <16 x i32>) #0
     30 
     31 ; CHECK-LABEL: f2:
     32 ; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
     33 
     34 define void @f2(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
     35 b0:
     36   %v0 = bitcast <16 x i32> %a0 to <512 x i1>
     37   tail call void @llvm.hexagon.V6.vS32b.nt.qpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
     38   ret void
     39 }
     40 
     41 ; Function Attrs: argmemonly nounwind
     42 declare void @llvm.hexagon.V6.vS32b.nt.qpred.ai(<512 x i1>, i8*, <16 x i32>) #0
     43 
     44 ; CHECK-LABEL: f3:
     45 ; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
     46 
     47 define void @f3(<16 x i32> %a0, i8* %a1, <16 x i32> %a2) local_unnamed_addr {
     48 b0:
     49   %v0 = bitcast <16 x i32> %a0 to <512 x i1>
     50   tail call void @llvm.hexagon.V6.vS32b.nt.nqpred.ai(<512 x i1> %v0, i8* %a1, <16 x i32> %a2)
     51   ret void
     52 }
     53 
     54 ; Function Attrs: argmemonly nounwind
     55 declare void @llvm.hexagon.V6.vS32b.nt.nqpred.ai(<512 x i1>, i8*, <16 x i32>) #0
     56 
     57 attributes #0 = { argmemonly nounwind }
     58