1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; Test that we compile the HVX dual output intrinsics. 4 5 ; CHECK-LABEL: f0: 6 ; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry 7 define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 { 8 b0: 9 %v0 = bitcast i8* %a2 to <512 x i1>* 10 %v1 = load <512 x i1>, <512 x i1>* %v0, align 64 11 %v2 = tail call { <16 x i32>, <512 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <512 x i1> %v1) 12 %v3 = extractvalue { <16 x i32>, <512 x i1> } %v2, 0 13 ret <16 x i32> %v3 14 } 15 16 ; CHECK-LABEL: f1: 17 ; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry 18 define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 { 19 b0: 20 %v0 = bitcast i8* %a2 to <512 x i1>* 21 %v1 = load <512 x i1>, <512 x i1>* %v0, align 64 22 %v2 = tail call { <16 x i32>, <512 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <512 x i1> %v1) 23 %v3 = extractvalue { <16 x i32>, <512 x i1> } %v2, 0 24 ret <16 x i32> %v3 25 } 26 27 ; Function Attrs: nounwind readnone 28 declare { <16 x i32>, <512 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <512 x i1>) #1 29 30 ; Function Attrs: nounwind readnone 31 declare { <16 x i32>, <512 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32>, <16 x i32>, <512 x i1>) #1 32 33 attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" } 34 attributes #1 = { nounwind readnone } 35
