1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; Test that V_vzero and W_vzero intrinsics work. The W_vzero intrinsic was added 4 ; for v65/hvx. 5 6 7 ; CHECK-LABEL: f0: 8 ; CHECK: [[VREG1:v([0-9]+)]] = vxor([[VREG1]],[[VREG1]]) 9 define void @f0(i16** nocapture %a0) #0 { 10 b0: 11 %v0 = bitcast i16** %a0 to <16 x i32>* 12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.vd0() 13 store <16 x i32> %v1, <16 x i32>* %v0, align 64 14 ret void 15 } 16 17 ; Function Attrs: nounwind readnone 18 declare <16 x i32> @llvm.hexagon.V6.vd0() #1 19 20 ; CHECK-LABEL: f1: 21 ; CHECK: [[VREG2:v([0-9]+):([0-9]+).w]] = vsub([[VREG2]],[[VREG2]]) 22 define void @f1(i16** nocapture %a0) #0 { 23 b0: 24 %v0 = bitcast i16** %a0 to <32 x i32>* 25 %v1 = tail call <32 x i32> @llvm.hexagon.V6.vdd0() 26 store <32 x i32> %v1, <32 x i32>* %v0, align 128 27 ret void 28 } 29 30 ; Function Attrs: nounwind readnone 31 declare <32 x i32> @llvm.hexagon.V6.vdd0() #1 32 33 attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" } 34 attributes #1 = { nounwind readnone } 35
