1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 4 ; The two loads based on %struct.0, loading two different data types 5 ; cause LSR to assume type "void" for the memory type. This would then 6 ; cause an assert in isLegalAddressingMode. Make sure we no longer crash. 7 8 target triple = "hexagon" 9 10 %struct.0 = type { i8*, i8, %union.anon.0 } 11 %union.anon.0 = type { i8* } 12 13 define hidden fastcc void @fred() unnamed_addr #0 { 14 entry: 15 br i1 undef, label %while.end, label %while.body.lr.ph 16 17 while.body.lr.ph: ; preds = %entry 18 br label %while.body 19 20 while.body: ; preds = %exit.2, %while.body.lr.ph 21 %lsr.iv = phi %struct.0* [ %cgep22, %exit.2 ], [ undef, %while.body.lr.ph ] 22 switch i32 undef, label %exit [ 23 i32 1, label %sw.bb.i 24 i32 2, label %sw.bb3.i 25 ] 26 27 sw.bb.i: ; preds = %while.body 28 unreachable 29 30 sw.bb3.i: ; preds = %while.body 31 unreachable 32 33 exit: ; preds = %while.body 34 switch i32 undef, label %exit.2 [ 35 i32 1, label %sw.bb.i17 36 i32 2, label %sw.bb3.i20 37 ] 38 39 sw.bb.i17: ; preds = %.exit 40 %0 = bitcast %struct.0* %lsr.iv to i32* 41 %1 = load i32, i32* %0, align 4 42 unreachable 43 44 sw.bb3.i20: ; preds = %exit 45 %2 = bitcast %struct.0* %lsr.iv to i8** 46 %3 = load i8*, i8** %2, align 4 47 unreachable 48 49 exit.2: ; preds = %exit 50 %cgep22 = getelementptr %struct.0, %struct.0* %lsr.iv, i32 1 51 br label %while.body 52 53 while.end: ; preds = %entry 54 ret void 55 } 56 57 attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" } 58 59
