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      1 ; RUN: llc -march=hexagon < %s | FileCheck %s
      2 
      3 @data1 = external global [2 x [31 x i8]], align 8
      4 @data2 = external global [2 x [91 x i8]], align 8
      5 
      6 ; CHECK-LABEL: Prefer_M4_or_andn:
      7 ; CHECK: r2 |= and(r0,~r1)
      8 define i32 @Prefer_M4_or_andn(i32 %a0, i32 %a1, i32 %a2) #0 {
      9 b3:
     10   %v4 = xor i32 %a1, -1
     11   %v5 = shl i32 %a2, 5
     12   %v6 = and i32 %a0, %v4
     13   %v7 = or i32 %v6, %v5
     14   ret i32 %v7
     15 }
     16 
     17 ; CHECK-LABEL: Prefer_M4_mpyri_addi:
     18 ; CHECK: add(##data1,mpyi(r0,#31))
     19 define i32 @Prefer_M4_mpyri_addi(i32 %a0) #0 {
     20 b1:
     21   %v2 = getelementptr inbounds [2 x [31 x i8]], [2 x [31 x i8]]* @data1, i32 0, i32 %a0
     22   %v3 = ptrtoint [31 x i8]* %v2 to i32
     23   ret i32 %v3
     24 }
     25 
     26 ; CHECK-LABEL: Prefer_M4_mpyrr_addi:
     27 ; CHECK: add(##data2,mpyi(r0,r1))
     28 define i32 @Prefer_M4_mpyrr_addi(i32 %a0) #0 {
     29 b1:
     30   %v2 = getelementptr inbounds [2 x [91 x i8]], [2 x [91 x i8]]* @data2, i32 0, i32 %a0
     31   %v3 = ptrtoint [91 x i8]* %v2 to i32
     32   ret i32 %v3
     33 }
     34 
     35 ; CHECK-LABEL: Prefer_S2_tstbit_r:
     36 ; CHECK: p0 = tstbit(r0,r1)
     37 define i32 @Prefer_S2_tstbit_r(i32 %a0, i32 %a1) #0 {
     38 b2:
     39   %v3 = shl i32 1, %a1
     40   %v4 = and i32 %a0, %v3
     41   %v5 = icmp ne i32 %v4, 0
     42   %v6 = zext i1 %v5 to i32
     43   ret i32 %v6
     44 }
     45 
     46 ; CHECK-LABEL: Prefer_S2_ntstbit_r:
     47 ; CHECK: p0 = !tstbit(r0,r1)
     48 define i32 @Prefer_S2_ntstbit_r(i32 %a0, i32 %a1) #0 {
     49 b2:
     50   %v3 = shl i32 1, %a1
     51   %v4 = and i32 %a0, %v3
     52   %v5 = icmp eq i32 %v4, 0
     53   %v6 = zext i1 %v5 to i32
     54   ret i32 %v6
     55 }
     56 
     57 ; CHECK-LABEL: Prefer_L2_loadrub_io:
     58 ; CHECK: memub(r0+#65)
     59 define i64 @Prefer_L2_loadrub_io(i8* %a0) #0 {
     60 b1:
     61   %v2 = getelementptr i8, i8* %a0, i32 65
     62   %v3 = load i8, i8* %v2
     63   %v4 = zext i8 %v3 to i64
     64   ret i64 %v4
     65 }
     66 
     67 attributes #0 = { optnone noinline nounwind readnone }
     68