1 ; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s 2 3 ; Check that zero-extends of short boolean vectors are done correctly. 4 ; These are not the only possible instruction sequences, so if something 5 ; changes, the tests should be changed as well. 6 7 ; CHECK-LABEL: f0: 8 ; CHECK-DAG: r[[D00:([0-9]+:[0-9]+)]] = vsxtbh(r0) 9 ; CHECK-DAG: r[[D01:([0-9]+:[0-9]+)]] = vsxtbh(r1) 10 ; CHECK: p[[P00:[0-3]]] = vcmph.gt(r[[D01]],r[[D00]]) 11 ; CHECK: r{{[0-9]+}}:[[R00:[0-9]+]] = mask(p[[P00]]) 12 ; CHECK: r0 = and(r[[R00]],##16843009) 13 define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1) #0 { 14 b0: 15 %v0 = icmp slt <4 x i8> %a0, %a1 16 %v1 = zext <4 x i1> %v0 to <4 x i8> 17 ret <4 x i8> %v1 18 } 19 20 ; CHECK-LABEL: f1: 21 ; CHECK-DAG: r[[D10:([0-9]+:[0-9]+)]] = vsxthw(r0) 22 ; CHECK-DAG: r[[D11:([0-9]+:[0-9]+)]] = vsxthw(r1) 23 ; CHECK: p[[P10:[0-3]]] = vcmpw.gt(r[[D11]],r[[D10]]) 24 ; CHECK: r{{[0-9]+}}:[[R10:[0-9]+]] = mask(p[[P10]]) 25 ; CHECK: r0 = and(r[[R10]],##65537) 26 define <2 x i16> @f1(<2 x i16> %a0, <2 x i16> %a1) #0 { 27 b0: 28 %v0 = icmp slt <2 x i16> %a0, %a1 29 %v1 = zext <2 x i1> %v0 to <2 x i16> 30 ret <2 x i16> %v1 31 } 32 33 ; CHECK-LABEL: f2: 34 ; CHECK-DAG: r[[D20:([0-9]+:[0-9]+)]] = CONST64(#72340172838076673) 35 ; CHECK-DAG: p[[P20:[0-3]]] = vcmpb.gt(r3:2,r1:0) 36 ; CHECK: r[[D21:([0-9]+:[0-9]+)]] = mask(p[[P20]]) 37 ; CHECK: r1:0 = and(r[[D21]],r[[D20]]) 38 define <8 x i8> @f2(<8 x i8> %a0, <8 x i8> %a1) #0 { 39 b0: 40 %v0 = icmp slt <8 x i8> %a0, %a1 41 %v1 = zext <8 x i1> %v0 to <8 x i8> 42 ret <8 x i8> %v1 43 } 44 45 ; CHECK-LABEL: f3: 46 ; CHECK-DAG: r[[D30:([0-9]+:[0-9]+)]] = CONST64(#281479271743489) 47 ; CHECK-DAG: p[[P30:[0-3]]] = vcmph.gt(r3:2,r1:0) 48 ; CHECK: r[[D31:([0-9]+:[0-9]+)]] = mask(p[[P30]]) 49 ; CHECK: r1:0 = and(r[[D31]],r[[D30]]) 50 define <4 x i16> @f3(<4 x i16> %a0, <4 x i16> %a1) #0 { 51 b0: 52 %v0 = icmp slt <4 x i16> %a0, %a1 53 %v1 = zext <4 x i1> %v0 to <4 x i16> 54 ret <4 x i16> %v1 55 } 56 57 ; CHECK-LABEL: f4: 58 ; CHECK-DAG: r[[D40:([0-9]+:[0-9]+)]] = combine(#1,#1) 59 ; CHECK-DAG: p[[P40:[0-3]]] = vcmpw.gt(r3:2,r1:0) 60 ; CHECK: r[[D41:([0-9]+:[0-9]+)]] = mask(p[[P40]]) 61 ; CHECK: r1:0 = and(r[[D41]],r[[D40]]) 62 define <2 x i32> @f4(<2 x i32> %a0, <2 x i32> %a1) #0 { 63 b0: 64 %v0 = icmp slt <2 x i32> %a0, %a1 65 %v1 = zext <2 x i1> %v0 to <2 x i32> 66 ret <2 x i32> %v1 67 } 68 69 attributes #0 = { nounwind readnone } 70
