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      1 ; RUN: llc -hexagon-emit-jt-text=true < %s | FileCheck %s
      2 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
      3 target triple = "hexagon-unknown--elf"
      4 
      5 ; CHECK: .text
      6 ; CHECK-NOT: .rodata
      7 ; CHECK: .word
      8 
      9 @lane0_pwr_st = global i32 0, align 4
     10 @lane1_pwr_st = global i32 0, align 4
     11 @lane2_pwr_st = global i32 0, align 4
     12 @lane3_pwr_st = global i32 0, align 4
     13 
     14 ; Function Attrs: noinline nounwind
     15 define void @test2(i32 %lane_id, i32 %rx_pwr_st) #0 {
     16 entry:
     17   %lane_id.addr = alloca i32, align 4
     18   %rx_pwr_st.addr = alloca i32, align 4
     19   store i32 %lane_id, i32* %lane_id.addr, align 4
     20   store i32 %rx_pwr_st, i32* %rx_pwr_st.addr, align 4
     21   %0 = load i32, i32* %lane_id.addr, align 4
     22   switch i32 %0, label %sw.epilog [
     23     i32 0, label %sw.bb
     24     i32 1, label %sw.bb1
     25     i32 2, label %sw.bb2
     26     i32 3, label %sw.bb3
     27     i32 15, label %sw.bb4
     28   ]
     29 
     30 sw.bb:                                            ; preds = %entry
     31   store i32 1, i32* @lane0_pwr_st, align 4
     32   br label %sw.epilog
     33 
     34 sw.bb1:                                           ; preds = %entry
     35   store i32 1, i32* @lane1_pwr_st, align 4
     36   br label %sw.epilog
     37 
     38 sw.bb2:                                           ; preds = %entry
     39   store i32 1, i32* @lane2_pwr_st, align 4
     40   br label %sw.epilog
     41 
     42 sw.bb3:                                           ; preds = %entry
     43   store i32 1, i32* @lane3_pwr_st, align 4
     44   br label %sw.epilog
     45 
     46 sw.bb4:                                           ; preds = %entry
     47   store i32 1, i32* @lane0_pwr_st, align 4
     48   store i32 1, i32* @lane1_pwr_st, align 4
     49   store i32 1, i32* @lane2_pwr_st, align 4
     50   store i32 1, i32* @lane3_pwr_st, align 4
     51   br label %sw.epilog
     52 
     53 sw.epilog:                                        ; preds = %entry, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
     54   ret void
     55 }
     56 
     57 attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
     58