1 ; Run -O2 to make sure that all the usual optimizations do happen before 2 ; the Hexagon loop idiom recognition runs. This is to check that we still 3 ; get this opportunity regardless of what happens before. 4 5 ; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s 6 7 target triple = "hexagon" 8 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 9 10 ; CHECK-LABEL: define zeroext i16 @pmpy_mod_lsr 11 ; There need to be two pmpy instructions. 12 ; CHECK: call i64 @llvm.hexagon.M4.pmpyw 13 ; CHECK: call i64 @llvm.hexagon.M4.pmpyw 14 15 define zeroext i16 @pmpy_mod_lsr(i8 zeroext %a0, i16 zeroext %a1) #0 { 16 b2: 17 br label %b3 18 19 b3: ; preds = %b44, %b2 20 %v4 = phi i8 [ %a0, %b2 ], [ %v19, %b44 ] 21 %v5 = phi i16 [ %a1, %b2 ], [ %v43, %b44 ] 22 %v6 = phi i8 [ 0, %b2 ], [ %v45, %b44 ] 23 %v7 = zext i8 %v6 to i32 24 %v8 = icmp slt i32 %v7, 8 25 br i1 %v8, label %b9, label %b46 26 27 b9: ; preds = %b3 28 %v10 = zext i8 %v4 to i32 29 %v11 = and i32 %v10, 1 30 %v12 = trunc i16 %v5 to i8 31 %v13 = zext i8 %v12 to i32 32 %v14 = and i32 %v13, 1 33 %v15 = xor i32 %v11, %v14 34 %v16 = trunc i32 %v15 to i8 35 %v17 = zext i8 %v4 to i32 36 %v18 = ashr i32 %v17, 1 37 %v19 = trunc i32 %v18 to i8 38 %v20 = zext i8 %v16 to i32 39 %v21 = icmp eq i32 %v20, 1 40 br i1 %v21, label %b22, label %b26 41 42 b22: ; preds = %b9 43 %v23 = zext i16 %v5 to i32 44 %v24 = xor i32 %v23, 16386 45 %v25 = trunc i32 %v24 to i16 46 br label %b27 47 48 b26: ; preds = %b9 49 br label %b27 50 51 b27: ; preds = %b26, %b22 52 %v28 = phi i16 [ %v25, %b22 ], [ %v5, %b26 ] 53 %v29 = phi i8 [ 1, %b22 ], [ 0, %b26 ] 54 %v30 = zext i16 %v28 to i32 55 %v31 = ashr i32 %v30, 1 56 %v32 = trunc i32 %v31 to i16 57 %v33 = icmp ne i8 %v29, 0 58 br i1 %v33, label %b34, label %b38 59 60 b34: ; preds = %b27 61 %v35 = zext i16 %v32 to i32 62 %v36 = or i32 %v35, 32768 63 %v37 = trunc i32 %v36 to i16 64 br label %b42 65 66 b38: ; preds = %b27 67 %v39 = zext i16 %v32 to i32 68 %v40 = and i32 %v39, 32767 69 %v41 = trunc i32 %v40 to i16 70 br label %b42 71 72 b42: ; preds = %b38, %b34 73 %v43 = phi i16 [ %v37, %b34 ], [ %v41, %b38 ] 74 br label %b44 75 76 b44: ; preds = %b42 77 %v45 = add i8 %v6, 1 78 br label %b3 79 80 b46: ; preds = %b3 81 ret i16 %v5 82 } 83 84 attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } 85
