1 ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s 2 ; Test that we do not exceed #u5 in memops. 3 ; CHECK-NOT: memb(r2+#0) -= #32 4 5 @g0 = unnamed_addr global i8 112, align 1 6 7 ; Function Attrs: norecurse nounwind 8 define fastcc void @f0() unnamed_addr #0 { 9 b0: 10 %v0 = load i8, i8* @g0, align 1, !tbaa !4 11 %v1 = zext i8 %v0 to i32 12 %v2 = mul nuw nsw i32 %v1, 9625 13 %v3 = and i32 %v2, 255 14 %v4 = mul nuw nsw i32 %v3, 9625 15 %v5 = and i32 %v4, 255 16 %v6 = trunc i32 %v5 to i8 17 store i8 %v6, i8* @g0, align 1, !tbaa !4 18 ret void 19 } 20 21 define i32 @f1() { 22 b0: 23 %v0 = load i8, i8* @g0, align 1, !tbaa !4 24 %v1 = zext i8 %v0 to i32 25 %v2 = add nuw nsw i32 %v1, 224 26 %v3 = trunc i32 %v2 to i8 27 store i8 %v3, i8* @g0, align 1, !tbaa !4 28 tail call fastcc void @f0() 29 %v4 = load i8, i8* @g0, align 1, !tbaa !4 30 %v5 = zext i8 %v4 to i32 31 ret i32 %v5 32 } 33 34 attributes #0 = { norecurse nounwind } 35 36 !llvm.module.flags = !{!0, !2} 37 38 !0 = !{i32 6, !"Target CPU", !1} 39 !1 = !{!"hexagonv55"} 40 !2 = !{i32 6, !"Target Features", !3} 41 !3 = !{!"-hvx"} 42 !4 = !{!5, !5, i64 0} 43 !5 = !{!"omnipotent char", !6, i64 0} 44 !6 = !{!"Simple C/C++ TBAA"} 45
