1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2 ; Generate MemOps for V4 and above. 3 4 define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { 5 entry: 6 ; CHECK-LABEL: memop_unsigned_char_add5: 7 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 8 %0 = load i8, i8* %p, align 1 9 %conv = zext i8 %0 to i32 10 %add = add nsw i32 %conv, 5 11 %conv1 = trunc i32 %add to i8 12 store i8 %conv1, i8* %p, align 1 13 ret void 14 } 15 16 define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { 17 entry: 18 ; CHECK-LABEL: memop_unsigned_char_add: 19 ; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} 20 %conv = zext i8 %x to i32 21 %0 = load i8, i8* %p, align 1 22 %conv1 = zext i8 %0 to i32 23 %add = add nsw i32 %conv1, %conv 24 %conv2 = trunc i32 %add to i8 25 store i8 %conv2, i8* %p, align 1 26 ret void 27 } 28 29 define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { 30 entry: 31 ; CHECK-LABEL: memop_unsigned_char_sub: 32 ; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 33 %conv = zext i8 %x to i32 34 %0 = load i8, i8* %p, align 1 35 %conv1 = zext i8 %0 to i32 36 %sub = sub nsw i32 %conv1, %conv 37 %conv2 = trunc i32 %sub to i8 38 store i8 %conv2, i8* %p, align 1 39 ret void 40 } 41 42 define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { 43 entry: 44 ; CHECK-LABEL: memop_unsigned_char_or: 45 ; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 46 %0 = load i8, i8* %p, align 1 47 %or3 = or i8 %0, %x 48 store i8 %or3, i8* %p, align 1 49 ret void 50 } 51 52 define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { 53 entry: 54 ; CHECK-LABEL: memop_unsigned_char_and: 55 ; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 56 %0 = load i8, i8* %p, align 1 57 %and3 = and i8 %0, %x 58 store i8 %and3, i8* %p, align 1 59 ret void 60 } 61 62 define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { 63 entry: 64 ; CHECK-LABEL: memop_unsigned_char_clrbit: 65 ; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) 66 %0 = load i8, i8* %p, align 1 67 %conv = zext i8 %0 to i32 68 %and = and i32 %conv, 223 69 %conv1 = trunc i32 %and to i8 70 store i8 %conv1, i8* %p, align 1 71 ret void 72 } 73 74 define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { 75 entry: 76 ; CHECK-LABEL: memop_unsigned_char_setbit: 77 ; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) 78 %0 = load i8, i8* %p, align 1 79 %conv = zext i8 %0 to i32 80 %or = or i32 %conv, 128 81 %conv1 = trunc i32 %or to i8 82 store i8 %conv1, i8* %p, align 1 83 ret void 84 } 85 86 define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { 87 entry: 88 ; CHECK-LABEL: memop_unsigned_char_add5_index: 89 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 90 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 91 %0 = load i8, i8* %add.ptr, align 1 92 %conv = zext i8 %0 to i32 93 %add = add nsw i32 %conv, 5 94 %conv1 = trunc i32 %add to i8 95 store i8 %conv1, i8* %add.ptr, align 1 96 ret void 97 } 98 99 define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 100 entry: 101 ; CHECK-LABEL: memop_unsigned_char_add_index: 102 ; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} 103 %conv = zext i8 %x to i32 104 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 105 %0 = load i8, i8* %add.ptr, align 1 106 %conv1 = zext i8 %0 to i32 107 %add = add nsw i32 %conv1, %conv 108 %conv2 = trunc i32 %add to i8 109 store i8 %conv2, i8* %add.ptr, align 1 110 ret void 111 } 112 113 define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 114 entry: 115 ; CHECK-LABEL: memop_unsigned_char_sub_index: 116 ; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 117 %conv = zext i8 %x to i32 118 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 119 %0 = load i8, i8* %add.ptr, align 1 120 %conv1 = zext i8 %0 to i32 121 %sub = sub nsw i32 %conv1, %conv 122 %conv2 = trunc i32 %sub to i8 123 store i8 %conv2, i8* %add.ptr, align 1 124 ret void 125 } 126 127 define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 128 entry: 129 ; CHECK-LABEL: memop_unsigned_char_or_index: 130 ; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 131 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 132 %0 = load i8, i8* %add.ptr, align 1 133 %or3 = or i8 %0, %x 134 store i8 %or3, i8* %add.ptr, align 1 135 ret void 136 } 137 138 define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 139 entry: 140 ; CHECK-LABEL: memop_unsigned_char_and_index: 141 ; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 142 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 143 %0 = load i8, i8* %add.ptr, align 1 144 %and3 = and i8 %0, %x 145 store i8 %and3, i8* %add.ptr, align 1 146 ret void 147 } 148 149 define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { 150 entry: 151 ; CHECK-LABEL: memop_unsigned_char_clrbit_index: 152 ; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) 153 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 154 %0 = load i8, i8* %add.ptr, align 1 155 %conv = zext i8 %0 to i32 156 %and = and i32 %conv, 223 157 %conv1 = trunc i32 %and to i8 158 store i8 %conv1, i8* %add.ptr, align 1 159 ret void 160 } 161 162 define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { 163 entry: 164 ; CHECK-LABEL: memop_unsigned_char_setbit_index: 165 ; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) 166 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 167 %0 = load i8, i8* %add.ptr, align 1 168 %conv = zext i8 %0 to i32 169 %or = or i32 %conv, 128 170 %conv1 = trunc i32 %or to i8 171 store i8 %conv1, i8* %add.ptr, align 1 172 ret void 173 } 174 175 define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { 176 entry: 177 ; CHECK-LABEL: memop_unsigned_char_add5_index5: 178 ; CHECK: memb(r{{[0-9]+}}+#5) += #5 179 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 180 %0 = load i8, i8* %add.ptr, align 1 181 %conv = zext i8 %0 to i32 182 %add = add nsw i32 %conv, 5 183 %conv1 = trunc i32 %add to i8 184 store i8 %conv1, i8* %add.ptr, align 1 185 ret void 186 } 187 188 define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 189 entry: 190 ; CHECK-LABEL: memop_unsigned_char_add_index5: 191 ; CHECK: memb(r{{[0-9]+}}+#5) += r{{[0-9]+}} 192 %conv = zext i8 %x to i32 193 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 194 %0 = load i8, i8* %add.ptr, align 1 195 %conv1 = zext i8 %0 to i32 196 %add = add nsw i32 %conv1, %conv 197 %conv2 = trunc i32 %add to i8 198 store i8 %conv2, i8* %add.ptr, align 1 199 ret void 200 } 201 202 define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 203 entry: 204 ; CHECK-LABEL: memop_unsigned_char_sub_index5: 205 ; CHECK: memb(r{{[0-9]+}}+#5) -= r{{[0-9]+}} 206 %conv = zext i8 %x to i32 207 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 208 %0 = load i8, i8* %add.ptr, align 1 209 %conv1 = zext i8 %0 to i32 210 %sub = sub nsw i32 %conv1, %conv 211 %conv2 = trunc i32 %sub to i8 212 store i8 %conv2, i8* %add.ptr, align 1 213 ret void 214 } 215 216 define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 217 entry: 218 ; CHECK-LABEL: memop_unsigned_char_or_index5: 219 ; CHECK: memb(r{{[0-9]+}}+#5) |= r{{[0-9]+}} 220 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 221 %0 = load i8, i8* %add.ptr, align 1 222 %or3 = or i8 %0, %x 223 store i8 %or3, i8* %add.ptr, align 1 224 ret void 225 } 226 227 define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 228 entry: 229 ; CHECK-LABEL: memop_unsigned_char_and_index5: 230 ; CHECK: memb(r{{[0-9]+}}+#5) &= r{{[0-9]+}} 231 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 232 %0 = load i8, i8* %add.ptr, align 1 233 %and3 = and i8 %0, %x 234 store i8 %and3, i8* %add.ptr, align 1 235 ret void 236 } 237 238 define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { 239 entry: 240 ; CHECK-LABEL: memop_unsigned_char_clrbit_index5: 241 ; CHECK: memb(r{{[0-9]+}}+#5) = clrbit(#5) 242 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 243 %0 = load i8, i8* %add.ptr, align 1 244 %conv = zext i8 %0 to i32 245 %and = and i32 %conv, 223 246 %conv1 = trunc i32 %and to i8 247 store i8 %conv1, i8* %add.ptr, align 1 248 ret void 249 } 250 251 define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { 252 entry: 253 ; CHECK-LABEL: memop_unsigned_char_setbit_index5: 254 ; CHECK: memb(r{{[0-9]+}}+#5) = setbit(#7) 255 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 256 %0 = load i8, i8* %add.ptr, align 1 257 %conv = zext i8 %0 to i32 258 %or = or i32 %conv, 128 259 %conv1 = trunc i32 %or to i8 260 store i8 %conv1, i8* %add.ptr, align 1 261 ret void 262 } 263 264 define void @memop_signed_char_add5(i8* nocapture %p) nounwind { 265 entry: 266 ; CHECK-LABEL: memop_signed_char_add5: 267 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 268 %0 = load i8, i8* %p, align 1 269 %conv2 = zext i8 %0 to i32 270 %add = add nsw i32 %conv2, 5 271 %conv1 = trunc i32 %add to i8 272 store i8 %conv1, i8* %p, align 1 273 ret void 274 } 275 276 define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { 277 entry: 278 ; CHECK-LABEL: memop_signed_char_add: 279 ; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} 280 %conv4 = zext i8 %x to i32 281 %0 = load i8, i8* %p, align 1 282 %conv13 = zext i8 %0 to i32 283 %add = add nsw i32 %conv13, %conv4 284 %conv2 = trunc i32 %add to i8 285 store i8 %conv2, i8* %p, align 1 286 ret void 287 } 288 289 define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { 290 entry: 291 ; CHECK-LABEL: memop_signed_char_sub: 292 ; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 293 %conv4 = zext i8 %x to i32 294 %0 = load i8, i8* %p, align 1 295 %conv13 = zext i8 %0 to i32 296 %sub = sub nsw i32 %conv13, %conv4 297 %conv2 = trunc i32 %sub to i8 298 store i8 %conv2, i8* %p, align 1 299 ret void 300 } 301 302 define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { 303 entry: 304 ; CHECK-LABEL: memop_signed_char_or: 305 ; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 306 %0 = load i8, i8* %p, align 1 307 %or3 = or i8 %0, %x 308 store i8 %or3, i8* %p, align 1 309 ret void 310 } 311 312 define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { 313 entry: 314 ; CHECK-LABEL: memop_signed_char_and: 315 ; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 316 %0 = load i8, i8* %p, align 1 317 %and3 = and i8 %0, %x 318 store i8 %and3, i8* %p, align 1 319 ret void 320 } 321 322 define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { 323 entry: 324 ; CHECK-LABEL: memop_signed_char_clrbit: 325 ; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) 326 %0 = load i8, i8* %p, align 1 327 %conv2 = zext i8 %0 to i32 328 %and = and i32 %conv2, 223 329 %conv1 = trunc i32 %and to i8 330 store i8 %conv1, i8* %p, align 1 331 ret void 332 } 333 334 define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { 335 entry: 336 ; CHECK-LABEL: memop_signed_char_setbit: 337 ; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) 338 %0 = load i8, i8* %p, align 1 339 %conv2 = zext i8 %0 to i32 340 %or = or i32 %conv2, 128 341 %conv1 = trunc i32 %or to i8 342 store i8 %conv1, i8* %p, align 1 343 ret void 344 } 345 346 define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { 347 entry: 348 ; CHECK-LABEL: memop_signed_char_add5_index: 349 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 350 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 351 %0 = load i8, i8* %add.ptr, align 1 352 %conv2 = zext i8 %0 to i32 353 %add = add nsw i32 %conv2, 5 354 %conv1 = trunc i32 %add to i8 355 store i8 %conv1, i8* %add.ptr, align 1 356 ret void 357 } 358 359 define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 360 entry: 361 ; CHECK-LABEL: memop_signed_char_add_index: 362 ; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} 363 %conv4 = zext i8 %x to i32 364 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 365 %0 = load i8, i8* %add.ptr, align 1 366 %conv13 = zext i8 %0 to i32 367 %add = add nsw i32 %conv13, %conv4 368 %conv2 = trunc i32 %add to i8 369 store i8 %conv2, i8* %add.ptr, align 1 370 ret void 371 } 372 373 define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 374 entry: 375 ; CHECK-LABEL: memop_signed_char_sub_index: 376 ; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 377 %conv4 = zext i8 %x to i32 378 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 379 %0 = load i8, i8* %add.ptr, align 1 380 %conv13 = zext i8 %0 to i32 381 %sub = sub nsw i32 %conv13, %conv4 382 %conv2 = trunc i32 %sub to i8 383 store i8 %conv2, i8* %add.ptr, align 1 384 ret void 385 } 386 387 define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 388 entry: 389 ; CHECK-LABEL: memop_signed_char_or_index: 390 ; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 391 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 392 %0 = load i8, i8* %add.ptr, align 1 393 %or3 = or i8 %0, %x 394 store i8 %or3, i8* %add.ptr, align 1 395 ret void 396 } 397 398 define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 399 entry: 400 ; CHECK-LABEL: memop_signed_char_and_index: 401 ; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 402 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 403 %0 = load i8, i8* %add.ptr, align 1 404 %and3 = and i8 %0, %x 405 store i8 %and3, i8* %add.ptr, align 1 406 ret void 407 } 408 409 define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { 410 entry: 411 ; CHECK-LABEL: memop_signed_char_clrbit_index: 412 ; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) 413 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 414 %0 = load i8, i8* %add.ptr, align 1 415 %conv2 = zext i8 %0 to i32 416 %and = and i32 %conv2, 223 417 %conv1 = trunc i32 %and to i8 418 store i8 %conv1, i8* %add.ptr, align 1 419 ret void 420 } 421 422 define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { 423 entry: 424 ; CHECK-LABEL: memop_signed_char_setbit_index: 425 ; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) 426 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i 427 %0 = load i8, i8* %add.ptr, align 1 428 %conv2 = zext i8 %0 to i32 429 %or = or i32 %conv2, 128 430 %conv1 = trunc i32 %or to i8 431 store i8 %conv1, i8* %add.ptr, align 1 432 ret void 433 } 434 435 define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { 436 entry: 437 ; CHECK-LABEL: memop_signed_char_add5_index5: 438 ; CHECK: memb(r{{[0-9]+}}+#5) += #5 439 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 440 %0 = load i8, i8* %add.ptr, align 1 441 %conv2 = zext i8 %0 to i32 442 %add = add nsw i32 %conv2, 5 443 %conv1 = trunc i32 %add to i8 444 store i8 %conv1, i8* %add.ptr, align 1 445 ret void 446 } 447 448 define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind { 449 entry: 450 ; CHECK-LABEL: memop_signed_char_add_index5: 451 ; CHECK: memb(r{{[0-9]+}}+#5) += r{{[0-9]+}} 452 %conv4 = zext i8 %x to i32 453 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 454 %0 = load i8, i8* %add.ptr, align 1 455 %conv13 = zext i8 %0 to i32 456 %add = add nsw i32 %conv13, %conv4 457 %conv2 = trunc i32 %add to i8 458 store i8 %conv2, i8* %add.ptr, align 1 459 ret void 460 } 461 462 define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind { 463 entry: 464 ; CHECK-LABEL: memop_signed_char_sub_index5: 465 ; CHECK: memb(r{{[0-9]+}}+#5) -= r{{[0-9]+}} 466 %conv4 = zext i8 %x to i32 467 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 468 %0 = load i8, i8* %add.ptr, align 1 469 %conv13 = zext i8 %0 to i32 470 %sub = sub nsw i32 %conv13, %conv4 471 %conv2 = trunc i32 %sub to i8 472 store i8 %conv2, i8* %add.ptr, align 1 473 ret void 474 } 475 476 define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { 477 entry: 478 ; CHECK-LABEL: memop_signed_char_or_index5: 479 ; CHECK: memb(r{{[0-9]+}}+#5) |= r{{[0-9]+}} 480 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 481 %0 = load i8, i8* %add.ptr, align 1 482 %or3 = or i8 %0, %x 483 store i8 %or3, i8* %add.ptr, align 1 484 ret void 485 } 486 487 define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { 488 entry: 489 ; CHECK-LABEL: memop_signed_char_and_index5: 490 ; CHECK: memb(r{{[0-9]+}}+#5) &= r{{[0-9]+}} 491 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 492 %0 = load i8, i8* %add.ptr, align 1 493 %and3 = and i8 %0, %x 494 store i8 %and3, i8* %add.ptr, align 1 495 ret void 496 } 497 498 define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { 499 entry: 500 ; CHECK-LABEL: memop_signed_char_clrbit_index5: 501 ; CHECK: memb(r{{[0-9]+}}+#5) = clrbit(#5) 502 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 503 %0 = load i8, i8* %add.ptr, align 1 504 %conv2 = zext i8 %0 to i32 505 %and = and i32 %conv2, 223 506 %conv1 = trunc i32 %and to i8 507 store i8 %conv1, i8* %add.ptr, align 1 508 ret void 509 } 510 511 define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { 512 entry: 513 ; CHECK-LABEL: memop_signed_char_setbit_index5: 514 ; CHECK: memb(r{{[0-9]+}}+#5) = setbit(#7) 515 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 516 %0 = load i8, i8* %add.ptr, align 1 517 %conv2 = zext i8 %0 to i32 518 %or = or i32 %conv2, 128 519 %conv1 = trunc i32 %or to i8 520 store i8 %conv1, i8* %add.ptr, align 1 521 ret void 522 } 523 524 define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { 525 entry: 526 ; CHECK-LABEL: memop_unsigned_short_add5: 527 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 528 %0 = load i16, i16* %p, align 2 529 %conv = zext i16 %0 to i32 530 %add = add nsw i32 %conv, 5 531 %conv1 = trunc i32 %add to i16 532 store i16 %conv1, i16* %p, align 2 533 ret void 534 } 535 536 define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind { 537 entry: 538 ; CHECK-LABEL: memop_unsigned_short_add: 539 ; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} 540 %conv = zext i16 %x to i32 541 %0 = load i16, i16* %p, align 2 542 %conv1 = zext i16 %0 to i32 543 %add = add nsw i32 %conv1, %conv 544 %conv2 = trunc i32 %add to i16 545 store i16 %conv2, i16* %p, align 2 546 ret void 547 } 548 549 define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind { 550 entry: 551 ; CHECK-LABEL: memop_unsigned_short_sub: 552 ; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 553 %conv = zext i16 %x to i32 554 %0 = load i16, i16* %p, align 2 555 %conv1 = zext i16 %0 to i32 556 %sub = sub nsw i32 %conv1, %conv 557 %conv2 = trunc i32 %sub to i16 558 store i16 %conv2, i16* %p, align 2 559 ret void 560 } 561 562 define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { 563 entry: 564 ; CHECK-LABEL: memop_unsigned_short_or: 565 ; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 566 %0 = load i16, i16* %p, align 2 567 %or3 = or i16 %0, %x 568 store i16 %or3, i16* %p, align 2 569 ret void 570 } 571 572 define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { 573 entry: 574 ; CHECK-LABEL: memop_unsigned_short_and: 575 ; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 576 %0 = load i16, i16* %p, align 2 577 %and3 = and i16 %0, %x 578 store i16 %and3, i16* %p, align 2 579 ret void 580 } 581 582 define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { 583 entry: 584 ; CHECK-LABEL: memop_unsigned_short_clrbit: 585 ; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) 586 %0 = load i16, i16* %p, align 2 587 %conv = zext i16 %0 to i32 588 %and = and i32 %conv, 65503 589 %conv1 = trunc i32 %and to i16 590 store i16 %conv1, i16* %p, align 2 591 ret void 592 } 593 594 define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { 595 entry: 596 ; CHECK-LABEL: memop_unsigned_short_setbit: 597 ; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) 598 %0 = load i16, i16* %p, align 2 599 %conv = zext i16 %0 to i32 600 %or = or i32 %conv, 128 601 %conv1 = trunc i32 %or to i16 602 store i16 %conv1, i16* %p, align 2 603 ret void 604 } 605 606 define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { 607 entry: 608 ; CHECK-LABEL: memop_unsigned_short_add5_index: 609 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 610 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 611 %0 = load i16, i16* %add.ptr, align 2 612 %conv = zext i16 %0 to i32 613 %add = add nsw i32 %conv, 5 614 %conv1 = trunc i32 %add to i16 615 store i16 %conv1, i16* %add.ptr, align 2 616 ret void 617 } 618 619 define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 620 entry: 621 ; CHECK-LABEL: memop_unsigned_short_add_index: 622 ; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} 623 %conv = zext i16 %x to i32 624 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 625 %0 = load i16, i16* %add.ptr, align 2 626 %conv1 = zext i16 %0 to i32 627 %add = add nsw i32 %conv1, %conv 628 %conv2 = trunc i32 %add to i16 629 store i16 %conv2, i16* %add.ptr, align 2 630 ret void 631 } 632 633 define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 634 entry: 635 ; CHECK-LABEL: memop_unsigned_short_sub_index: 636 ; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 637 %conv = zext i16 %x to i32 638 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 639 %0 = load i16, i16* %add.ptr, align 2 640 %conv1 = zext i16 %0 to i32 641 %sub = sub nsw i32 %conv1, %conv 642 %conv2 = trunc i32 %sub to i16 643 store i16 %conv2, i16* %add.ptr, align 2 644 ret void 645 } 646 647 define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 648 entry: 649 ; CHECK-LABEL: memop_unsigned_short_or_index: 650 ; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 651 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 652 %0 = load i16, i16* %add.ptr, align 2 653 %or3 = or i16 %0, %x 654 store i16 %or3, i16* %add.ptr, align 2 655 ret void 656 } 657 658 define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 659 entry: 660 ; CHECK-LABEL: memop_unsigned_short_and_index: 661 ; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 662 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 663 %0 = load i16, i16* %add.ptr, align 2 664 %and3 = and i16 %0, %x 665 store i16 %and3, i16* %add.ptr, align 2 666 ret void 667 } 668 669 define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { 670 entry: 671 ; CHECK-LABEL: memop_unsigned_short_clrbit_index: 672 ; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) 673 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 674 %0 = load i16, i16* %add.ptr, align 2 675 %conv = zext i16 %0 to i32 676 %and = and i32 %conv, 65503 677 %conv1 = trunc i32 %and to i16 678 store i16 %conv1, i16* %add.ptr, align 2 679 ret void 680 } 681 682 define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { 683 entry: 684 ; CHECK-LABEL: memop_unsigned_short_setbit_index: 685 ; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) 686 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 687 %0 = load i16, i16* %add.ptr, align 2 688 %conv = zext i16 %0 to i32 689 %or = or i32 %conv, 128 690 %conv1 = trunc i32 %or to i16 691 store i16 %conv1, i16* %add.ptr, align 2 692 ret void 693 } 694 695 define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { 696 entry: 697 ; CHECK-LABEL: memop_unsigned_short_add5_index5: 698 ; CHECK: memh(r{{[0-9]+}}+#10) += #5 699 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 700 %0 = load i16, i16* %add.ptr, align 2 701 %conv = zext i16 %0 to i32 702 %add = add nsw i32 %conv, 5 703 %conv1 = trunc i32 %add to i16 704 store i16 %conv1, i16* %add.ptr, align 2 705 ret void 706 } 707 708 define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 709 entry: 710 ; CHECK-LABEL: memop_unsigned_short_add_index5: 711 ; CHECK: memh(r{{[0-9]+}}+#10) += r{{[0-9]+}} 712 %conv = zext i16 %x to i32 713 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 714 %0 = load i16, i16* %add.ptr, align 2 715 %conv1 = zext i16 %0 to i32 716 %add = add nsw i32 %conv1, %conv 717 %conv2 = trunc i32 %add to i16 718 store i16 %conv2, i16* %add.ptr, align 2 719 ret void 720 } 721 722 define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 723 entry: 724 ; CHECK-LABEL: memop_unsigned_short_sub_index5: 725 ; CHECK: memh(r{{[0-9]+}}+#10) -= r{{[0-9]+}} 726 %conv = zext i16 %x to i32 727 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 728 %0 = load i16, i16* %add.ptr, align 2 729 %conv1 = zext i16 %0 to i32 730 %sub = sub nsw i32 %conv1, %conv 731 %conv2 = trunc i32 %sub to i16 732 store i16 %conv2, i16* %add.ptr, align 2 733 ret void 734 } 735 736 define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 737 entry: 738 ; CHECK-LABEL: memop_unsigned_short_or_index5: 739 ; CHECK: memh(r{{[0-9]+}}+#10) |= r{{[0-9]+}} 740 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 741 %0 = load i16, i16* %add.ptr, align 2 742 %or3 = or i16 %0, %x 743 store i16 %or3, i16* %add.ptr, align 2 744 ret void 745 } 746 747 define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 748 entry: 749 ; CHECK-LABEL: memop_unsigned_short_and_index5: 750 ; CHECK: memh(r{{[0-9]+}}+#10) &= r{{[0-9]+}} 751 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 752 %0 = load i16, i16* %add.ptr, align 2 753 %and3 = and i16 %0, %x 754 store i16 %and3, i16* %add.ptr, align 2 755 ret void 756 } 757 758 define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { 759 entry: 760 ; CHECK-LABEL: memop_unsigned_short_clrbit_index5: 761 ; CHECK: memh(r{{[0-9]+}}+#10) = clrbit(#5) 762 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 763 %0 = load i16, i16* %add.ptr, align 2 764 %conv = zext i16 %0 to i32 765 %and = and i32 %conv, 65503 766 %conv1 = trunc i32 %and to i16 767 store i16 %conv1, i16* %add.ptr, align 2 768 ret void 769 } 770 771 define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { 772 entry: 773 ; CHECK-LABEL: memop_unsigned_short_setbit_index5: 774 ; CHECK: memh(r{{[0-9]+}}+#10) = setbit(#7) 775 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 776 %0 = load i16, i16* %add.ptr, align 2 777 %conv = zext i16 %0 to i32 778 %or = or i32 %conv, 128 779 %conv1 = trunc i32 %or to i16 780 store i16 %conv1, i16* %add.ptr, align 2 781 ret void 782 } 783 784 define void @memop_signed_short_add5(i16* nocapture %p) nounwind { 785 entry: 786 ; CHECK-LABEL: memop_signed_short_add5: 787 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 788 %0 = load i16, i16* %p, align 2 789 %conv2 = zext i16 %0 to i32 790 %add = add nsw i32 %conv2, 5 791 %conv1 = trunc i32 %add to i16 792 store i16 %conv1, i16* %p, align 2 793 ret void 794 } 795 796 define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind { 797 entry: 798 ; CHECK-LABEL: memop_signed_short_add: 799 ; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} 800 %conv4 = zext i16 %x to i32 801 %0 = load i16, i16* %p, align 2 802 %conv13 = zext i16 %0 to i32 803 %add = add nsw i32 %conv13, %conv4 804 %conv2 = trunc i32 %add to i16 805 store i16 %conv2, i16* %p, align 2 806 ret void 807 } 808 809 define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind { 810 entry: 811 ; CHECK-LABEL: memop_signed_short_sub: 812 ; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 813 %conv4 = zext i16 %x to i32 814 %0 = load i16, i16* %p, align 2 815 %conv13 = zext i16 %0 to i32 816 %sub = sub nsw i32 %conv13, %conv4 817 %conv2 = trunc i32 %sub to i16 818 store i16 %conv2, i16* %p, align 2 819 ret void 820 } 821 822 define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { 823 entry: 824 ; CHECK-LABEL: memop_signed_short_or: 825 ; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 826 %0 = load i16, i16* %p, align 2 827 %or3 = or i16 %0, %x 828 store i16 %or3, i16* %p, align 2 829 ret void 830 } 831 832 define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { 833 entry: 834 ; CHECK-LABEL: memop_signed_short_and: 835 ; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 836 %0 = load i16, i16* %p, align 2 837 %and3 = and i16 %0, %x 838 store i16 %and3, i16* %p, align 2 839 ret void 840 } 841 842 define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { 843 entry: 844 ; CHECK-LABEL: memop_signed_short_clrbit: 845 ; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) 846 %0 = load i16, i16* %p, align 2 847 %conv2 = zext i16 %0 to i32 848 %and = and i32 %conv2, 65503 849 %conv1 = trunc i32 %and to i16 850 store i16 %conv1, i16* %p, align 2 851 ret void 852 } 853 854 define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { 855 entry: 856 ; CHECK-LABEL: memop_signed_short_setbit: 857 ; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) 858 %0 = load i16, i16* %p, align 2 859 %conv2 = zext i16 %0 to i32 860 %or = or i32 %conv2, 128 861 %conv1 = trunc i32 %or to i16 862 store i16 %conv1, i16* %p, align 2 863 ret void 864 } 865 866 define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { 867 entry: 868 ; CHECK-LABEL: memop_signed_short_add5_index: 869 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 870 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 871 %0 = load i16, i16* %add.ptr, align 2 872 %conv2 = zext i16 %0 to i32 873 %add = add nsw i32 %conv2, 5 874 %conv1 = trunc i32 %add to i16 875 store i16 %conv1, i16* %add.ptr, align 2 876 ret void 877 } 878 879 define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 880 entry: 881 ; CHECK-LABEL: memop_signed_short_add_index: 882 ; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} 883 %conv4 = zext i16 %x to i32 884 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 885 %0 = load i16, i16* %add.ptr, align 2 886 %conv13 = zext i16 %0 to i32 887 %add = add nsw i32 %conv13, %conv4 888 %conv2 = trunc i32 %add to i16 889 store i16 %conv2, i16* %add.ptr, align 2 890 ret void 891 } 892 893 define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 894 entry: 895 ; CHECK-LABEL: memop_signed_short_sub_index: 896 ; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 897 %conv4 = zext i16 %x to i32 898 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 899 %0 = load i16, i16* %add.ptr, align 2 900 %conv13 = zext i16 %0 to i32 901 %sub = sub nsw i32 %conv13, %conv4 902 %conv2 = trunc i32 %sub to i16 903 store i16 %conv2, i16* %add.ptr, align 2 904 ret void 905 } 906 907 define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 908 entry: 909 ; CHECK-LABEL: memop_signed_short_or_index: 910 ; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 911 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 912 %0 = load i16, i16* %add.ptr, align 2 913 %or3 = or i16 %0, %x 914 store i16 %or3, i16* %add.ptr, align 2 915 ret void 916 } 917 918 define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 919 entry: 920 ; CHECK-LABEL: memop_signed_short_and_index: 921 ; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 922 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 923 %0 = load i16, i16* %add.ptr, align 2 924 %and3 = and i16 %0, %x 925 store i16 %and3, i16* %add.ptr, align 2 926 ret void 927 } 928 929 define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { 930 entry: 931 ; CHECK-LABEL: memop_signed_short_clrbit_index: 932 ; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) 933 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 934 %0 = load i16, i16* %add.ptr, align 2 935 %conv2 = zext i16 %0 to i32 936 %and = and i32 %conv2, 65503 937 %conv1 = trunc i32 %and to i16 938 store i16 %conv1, i16* %add.ptr, align 2 939 ret void 940 } 941 942 define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { 943 entry: 944 ; CHECK-LABEL: memop_signed_short_setbit_index: 945 ; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) 946 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i 947 %0 = load i16, i16* %add.ptr, align 2 948 %conv2 = zext i16 %0 to i32 949 %or = or i32 %conv2, 128 950 %conv1 = trunc i32 %or to i16 951 store i16 %conv1, i16* %add.ptr, align 2 952 ret void 953 } 954 955 define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { 956 entry: 957 ; CHECK-LABEL: memop_signed_short_add5_index5: 958 ; CHECK: memh(r{{[0-9]+}}+#10) += #5 959 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 960 %0 = load i16, i16* %add.ptr, align 2 961 %conv2 = zext i16 %0 to i32 962 %add = add nsw i32 %conv2, 5 963 %conv1 = trunc i32 %add to i16 964 store i16 %conv1, i16* %add.ptr, align 2 965 ret void 966 } 967 968 define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind { 969 entry: 970 ; CHECK-LABEL: memop_signed_short_add_index5: 971 ; CHECK: memh(r{{[0-9]+}}+#10) += r{{[0-9]+}} 972 %conv4 = zext i16 %x to i32 973 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 974 %0 = load i16, i16* %add.ptr, align 2 975 %conv13 = zext i16 %0 to i32 976 %add = add nsw i32 %conv13, %conv4 977 %conv2 = trunc i32 %add to i16 978 store i16 %conv2, i16* %add.ptr, align 2 979 ret void 980 } 981 982 define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind { 983 entry: 984 ; CHECK-LABEL: memop_signed_short_sub_index5: 985 ; CHECK: memh(r{{[0-9]+}}+#10) -= r{{[0-9]+}} 986 %conv4 = zext i16 %x to i32 987 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 988 %0 = load i16, i16* %add.ptr, align 2 989 %conv13 = zext i16 %0 to i32 990 %sub = sub nsw i32 %conv13, %conv4 991 %conv2 = trunc i32 %sub to i16 992 store i16 %conv2, i16* %add.ptr, align 2 993 ret void 994 } 995 996 define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { 997 entry: 998 ; CHECK-LABEL: memop_signed_short_or_index5: 999 ; CHECK: memh(r{{[0-9]+}}+#10) |= r{{[0-9]+}} 1000 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 1001 %0 = load i16, i16* %add.ptr, align 2 1002 %or3 = or i16 %0, %x 1003 store i16 %or3, i16* %add.ptr, align 2 1004 ret void 1005 } 1006 1007 define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { 1008 entry: 1009 ; CHECK-LABEL: memop_signed_short_and_index5: 1010 ; CHECK: memh(r{{[0-9]+}}+#10) &= r{{[0-9]+}} 1011 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 1012 %0 = load i16, i16* %add.ptr, align 2 1013 %and3 = and i16 %0, %x 1014 store i16 %and3, i16* %add.ptr, align 2 1015 ret void 1016 } 1017 1018 define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { 1019 entry: 1020 ; CHECK-LABEL: memop_signed_short_clrbit_index5: 1021 ; CHECK: memh(r{{[0-9]+}}+#10) = clrbit(#5) 1022 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 1023 %0 = load i16, i16* %add.ptr, align 2 1024 %conv2 = zext i16 %0 to i32 1025 %and = and i32 %conv2, 65503 1026 %conv1 = trunc i32 %and to i16 1027 store i16 %conv1, i16* %add.ptr, align 2 1028 ret void 1029 } 1030 1031 define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { 1032 entry: 1033 ; CHECK-LABEL: memop_signed_short_setbit_index5: 1034 ; CHECK: memh(r{{[0-9]+}}+#10) = setbit(#7) 1035 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 1036 %0 = load i16, i16* %add.ptr, align 2 1037 %conv2 = zext i16 %0 to i32 1038 %or = or i32 %conv2, 128 1039 %conv1 = trunc i32 %or to i16 1040 store i16 %conv1, i16* %add.ptr, align 2 1041 ret void 1042 } 1043 1044 define void @memop_signed_int_add5(i32* nocapture %p) nounwind { 1045 entry: 1046 ; CHECK-LABEL: memop_signed_int_add5: 1047 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 1048 %0 = load i32, i32* %p, align 4 1049 %add = add i32 %0, 5 1050 store i32 %add, i32* %p, align 4 1051 ret void 1052 } 1053 1054 define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { 1055 entry: 1056 ; CHECK-LABEL: memop_signed_int_add: 1057 ; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} 1058 %0 = load i32, i32* %p, align 4 1059 %add = add i32 %0, %x 1060 store i32 %add, i32* %p, align 4 1061 ret void 1062 } 1063 1064 define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { 1065 entry: 1066 ; CHECK-LABEL: memop_signed_int_sub: 1067 ; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 1068 %0 = load i32, i32* %p, align 4 1069 %sub = sub i32 %0, %x 1070 store i32 %sub, i32* %p, align 4 1071 ret void 1072 } 1073 1074 define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { 1075 entry: 1076 ; CHECK-LABEL: memop_signed_int_or: 1077 ; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 1078 %0 = load i32, i32* %p, align 4 1079 %or = or i32 %0, %x 1080 store i32 %or, i32* %p, align 4 1081 ret void 1082 } 1083 1084 define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { 1085 entry: 1086 ; CHECK-LABEL: memop_signed_int_and: 1087 ; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 1088 %0 = load i32, i32* %p, align 4 1089 %and = and i32 %0, %x 1090 store i32 %and, i32* %p, align 4 1091 ret void 1092 } 1093 1094 define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { 1095 entry: 1096 ; CHECK-LABEL: memop_signed_int_clrbit: 1097 ; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) 1098 %0 = load i32, i32* %p, align 4 1099 %and = and i32 %0, -33 1100 store i32 %and, i32* %p, align 4 1101 ret void 1102 } 1103 1104 define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { 1105 entry: 1106 ; CHECK-LABEL: memop_signed_int_setbit: 1107 ; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) 1108 %0 = load i32, i32* %p, align 4 1109 %or = or i32 %0, 128 1110 store i32 %or, i32* %p, align 4 1111 ret void 1112 } 1113 1114 define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { 1115 entry: 1116 ; CHECK-LABEL: memop_signed_int_add5_index: 1117 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 1118 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1119 %0 = load i32, i32* %add.ptr, align 4 1120 %add = add i32 %0, 5 1121 store i32 %add, i32* %add.ptr, align 4 1122 ret void 1123 } 1124 1125 define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1126 entry: 1127 ; CHECK-LABEL: memop_signed_int_add_index: 1128 ; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} 1129 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1130 %0 = load i32, i32* %add.ptr, align 4 1131 %add = add i32 %0, %x 1132 store i32 %add, i32* %add.ptr, align 4 1133 ret void 1134 } 1135 1136 define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1137 entry: 1138 ; CHECK-LABEL: memop_signed_int_sub_index: 1139 ; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 1140 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1141 %0 = load i32, i32* %add.ptr, align 4 1142 %sub = sub i32 %0, %x 1143 store i32 %sub, i32* %add.ptr, align 4 1144 ret void 1145 } 1146 1147 define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1148 entry: 1149 ; CHECK-LABEL: memop_signed_int_or_index: 1150 ; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 1151 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1152 %0 = load i32, i32* %add.ptr, align 4 1153 %or = or i32 %0, %x 1154 store i32 %or, i32* %add.ptr, align 4 1155 ret void 1156 } 1157 1158 define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1159 entry: 1160 ; CHECK-LABEL: memop_signed_int_and_index: 1161 ; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 1162 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1163 %0 = load i32, i32* %add.ptr, align 4 1164 %and = and i32 %0, %x 1165 store i32 %and, i32* %add.ptr, align 4 1166 ret void 1167 } 1168 1169 define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { 1170 entry: 1171 ; CHECK-LABEL: memop_signed_int_clrbit_index: 1172 ; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) 1173 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1174 %0 = load i32, i32* %add.ptr, align 4 1175 %and = and i32 %0, -33 1176 store i32 %and, i32* %add.ptr, align 4 1177 ret void 1178 } 1179 1180 define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { 1181 entry: 1182 ; CHECK-LABEL: memop_signed_int_setbit_index: 1183 ; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) 1184 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1185 %0 = load i32, i32* %add.ptr, align 4 1186 %or = or i32 %0, 128 1187 store i32 %or, i32* %add.ptr, align 4 1188 ret void 1189 } 1190 1191 define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { 1192 entry: 1193 ; CHECK-LABEL: memop_signed_int_add5_index5: 1194 ; CHECK: memw(r{{[0-9]+}}+#20) += #5 1195 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1196 %0 = load i32, i32* %add.ptr, align 4 1197 %add = add i32 %0, 5 1198 store i32 %add, i32* %add.ptr, align 4 1199 ret void 1200 } 1201 1202 define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { 1203 entry: 1204 ; CHECK-LABEL: memop_signed_int_add_index5: 1205 ; CHECK: memw(r{{[0-9]+}}+#20) += r{{[0-9]+}} 1206 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1207 %0 = load i32, i32* %add.ptr, align 4 1208 %add = add i32 %0, %x 1209 store i32 %add, i32* %add.ptr, align 4 1210 ret void 1211 } 1212 1213 define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { 1214 entry: 1215 ; CHECK-LABEL: memop_signed_int_sub_index5: 1216 ; CHECK: memw(r{{[0-9]+}}+#20) -= r{{[0-9]+}} 1217 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1218 %0 = load i32, i32* %add.ptr, align 4 1219 %sub = sub i32 %0, %x 1220 store i32 %sub, i32* %add.ptr, align 4 1221 ret void 1222 } 1223 1224 define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { 1225 entry: 1226 ; CHECK-LABEL: memop_signed_int_or_index5: 1227 ; CHECK: memw(r{{[0-9]+}}+#20) |= r{{[0-9]+}} 1228 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1229 %0 = load i32, i32* %add.ptr, align 4 1230 %or = or i32 %0, %x 1231 store i32 %or, i32* %add.ptr, align 4 1232 ret void 1233 } 1234 1235 define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { 1236 entry: 1237 ; CHECK-LABEL: memop_signed_int_and_index5: 1238 ; CHECK: memw(r{{[0-9]+}}+#20) &= r{{[0-9]+}} 1239 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1240 %0 = load i32, i32* %add.ptr, align 4 1241 %and = and i32 %0, %x 1242 store i32 %and, i32* %add.ptr, align 4 1243 ret void 1244 } 1245 1246 define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { 1247 entry: 1248 ; CHECK-LABEL: memop_signed_int_clrbit_index5: 1249 ; CHECK: memw(r{{[0-9]+}}+#20) = clrbit(#5) 1250 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1251 %0 = load i32, i32* %add.ptr, align 4 1252 %and = and i32 %0, -33 1253 store i32 %and, i32* %add.ptr, align 4 1254 ret void 1255 } 1256 1257 define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { 1258 entry: 1259 ; CHECK-LABEL: memop_signed_int_setbit_index5: 1260 ; CHECK: memw(r{{[0-9]+}}+#20) = setbit(#7) 1261 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1262 %0 = load i32, i32* %add.ptr, align 4 1263 %or = or i32 %0, 128 1264 store i32 %or, i32* %add.ptr, align 4 1265 ret void 1266 } 1267 1268 define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { 1269 entry: 1270 ; CHECK-LABEL: memop_unsigned_int_add5: 1271 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 1272 %0 = load i32, i32* %p, align 4 1273 %add = add nsw i32 %0, 5 1274 store i32 %add, i32* %p, align 4 1275 ret void 1276 } 1277 1278 define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { 1279 entry: 1280 ; CHECK-LABEL: memop_unsigned_int_add: 1281 ; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} 1282 %0 = load i32, i32* %p, align 4 1283 %add = add nsw i32 %0, %x 1284 store i32 %add, i32* %p, align 4 1285 ret void 1286 } 1287 1288 define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { 1289 entry: 1290 ; CHECK-LABEL: memop_unsigned_int_sub: 1291 ; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 1292 %0 = load i32, i32* %p, align 4 1293 %sub = sub nsw i32 %0, %x 1294 store i32 %sub, i32* %p, align 4 1295 ret void 1296 } 1297 1298 define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { 1299 entry: 1300 ; CHECK-LABEL: memop_unsigned_int_or: 1301 ; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 1302 %0 = load i32, i32* %p, align 4 1303 %or = or i32 %0, %x 1304 store i32 %or, i32* %p, align 4 1305 ret void 1306 } 1307 1308 define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { 1309 entry: 1310 ; CHECK-LABEL: memop_unsigned_int_and: 1311 ; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 1312 %0 = load i32, i32* %p, align 4 1313 %and = and i32 %0, %x 1314 store i32 %and, i32* %p, align 4 1315 ret void 1316 } 1317 1318 define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { 1319 entry: 1320 ; CHECK-LABEL: memop_unsigned_int_clrbit: 1321 ; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) 1322 %0 = load i32, i32* %p, align 4 1323 %and = and i32 %0, -33 1324 store i32 %and, i32* %p, align 4 1325 ret void 1326 } 1327 1328 define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { 1329 entry: 1330 ; CHECK-LABEL: memop_unsigned_int_setbit: 1331 ; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) 1332 %0 = load i32, i32* %p, align 4 1333 %or = or i32 %0, 128 1334 store i32 %or, i32* %p, align 4 1335 ret void 1336 } 1337 1338 define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { 1339 entry: 1340 ; CHECK-LABEL: memop_unsigned_int_add5_index: 1341 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 1342 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1343 %0 = load i32, i32* %add.ptr, align 4 1344 %add = add nsw i32 %0, 5 1345 store i32 %add, i32* %add.ptr, align 4 1346 ret void 1347 } 1348 1349 define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1350 entry: 1351 ; CHECK-LABEL: memop_unsigned_int_add_index: 1352 ; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} 1353 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1354 %0 = load i32, i32* %add.ptr, align 4 1355 %add = add nsw i32 %0, %x 1356 store i32 %add, i32* %add.ptr, align 4 1357 ret void 1358 } 1359 1360 define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1361 entry: 1362 ; CHECK-LABEL: memop_unsigned_int_sub_index: 1363 ; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 1364 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1365 %0 = load i32, i32* %add.ptr, align 4 1366 %sub = sub nsw i32 %0, %x 1367 store i32 %sub, i32* %add.ptr, align 4 1368 ret void 1369 } 1370 1371 define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1372 entry: 1373 ; CHECK-LABEL: memop_unsigned_int_or_index: 1374 ; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 1375 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1376 %0 = load i32, i32* %add.ptr, align 4 1377 %or = or i32 %0, %x 1378 store i32 %or, i32* %add.ptr, align 4 1379 ret void 1380 } 1381 1382 define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1383 entry: 1384 ; CHECK-LABEL: memop_unsigned_int_and_index: 1385 ; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 1386 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1387 %0 = load i32, i32* %add.ptr, align 4 1388 %and = and i32 %0, %x 1389 store i32 %and, i32* %add.ptr, align 4 1390 ret void 1391 } 1392 1393 define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { 1394 entry: 1395 ; CHECK-LABEL: memop_unsigned_int_clrbit_index: 1396 ; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) 1397 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1398 %0 = load i32, i32* %add.ptr, align 4 1399 %and = and i32 %0, -33 1400 store i32 %and, i32* %add.ptr, align 4 1401 ret void 1402 } 1403 1404 define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { 1405 entry: 1406 ; CHECK-LABEL: memop_unsigned_int_setbit_index: 1407 ; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) 1408 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i 1409 %0 = load i32, i32* %add.ptr, align 4 1410 %or = or i32 %0, 128 1411 store i32 %or, i32* %add.ptr, align 4 1412 ret void 1413 } 1414 1415 define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { 1416 entry: 1417 ; CHECK-LABEL: memop_unsigned_int_add5_index5: 1418 ; CHECK: memw(r{{[0-9]+}}+#20) += #5 1419 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1420 %0 = load i32, i32* %add.ptr, align 4 1421 %add = add nsw i32 %0, 5 1422 store i32 %add, i32* %add.ptr, align 4 1423 ret void 1424 } 1425 1426 define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { 1427 entry: 1428 ; CHECK-LABEL: memop_unsigned_int_add_index5: 1429 ; CHECK: memw(r{{[0-9]+}}+#20) += r{{[0-9]+}} 1430 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1431 %0 = load i32, i32* %add.ptr, align 4 1432 %add = add nsw i32 %0, %x 1433 store i32 %add, i32* %add.ptr, align 4 1434 ret void 1435 } 1436 1437 define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { 1438 entry: 1439 ; CHECK-LABEL: memop_unsigned_int_sub_index5: 1440 ; CHECK: memw(r{{[0-9]+}}+#20) -= r{{[0-9]+}} 1441 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1442 %0 = load i32, i32* %add.ptr, align 4 1443 %sub = sub nsw i32 %0, %x 1444 store i32 %sub, i32* %add.ptr, align 4 1445 ret void 1446 } 1447 1448 define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { 1449 entry: 1450 ; CHECK-LABEL: memop_unsigned_int_or_index5: 1451 ; CHECK: memw(r{{[0-9]+}}+#20) |= r{{[0-9]+}} 1452 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1453 %0 = load i32, i32* %add.ptr, align 4 1454 %or = or i32 %0, %x 1455 store i32 %or, i32* %add.ptr, align 4 1456 ret void 1457 } 1458 1459 define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { 1460 entry: 1461 ; CHECK-LABEL: memop_unsigned_int_and_index5: 1462 ; CHECK: memw(r{{[0-9]+}}+#20) &= r{{[0-9]+}} 1463 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1464 %0 = load i32, i32* %add.ptr, align 4 1465 %and = and i32 %0, %x 1466 store i32 %and, i32* %add.ptr, align 4 1467 ret void 1468 } 1469 1470 define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { 1471 entry: 1472 ; CHECK-LABEL: memop_unsigned_int_clrbit_index5: 1473 ; CHECK: memw(r{{[0-9]+}}+#20) = clrbit(#5) 1474 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1475 %0 = load i32, i32* %add.ptr, align 4 1476 %and = and i32 %0, -33 1477 store i32 %and, i32* %add.ptr, align 4 1478 ret void 1479 } 1480 1481 define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { 1482 entry: 1483 ; CHECK-LABEL: memop_unsigned_int_setbit_index5: 1484 ; CHECK: memw(r{{[0-9]+}}+#20) = setbit(#7) 1485 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 1486 %0 = load i32, i32* %add.ptr, align 4 1487 %or = or i32 %0, 128 1488 store i32 %or, i32* %add.ptr, align 4 1489 ret void 1490 } 1491
