1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 @g0 = common global i8 0, align 1 4 @g1 = common global i8 0, align 1 5 @g2 = common global i16 0, align 2 6 @g3 = common global i16 0, align 2 7 @g4 = common global i32 0, align 4 8 @g5 = common global i32 0, align 4 9 10 ; CHECK-LABEL: f0: 11 ; CHECK: memb(r{{[0-9]+}}+#0) += #1 12 define void @f0() #0 { 13 b0: 14 %v0 = load i8, i8* @g0, align 1, !tbaa !0 15 %v1 = add i8 %v0, 1 16 store i8 %v1, i8* @g0, align 1, !tbaa !0 17 ret void 18 } 19 20 ; CHECK-LABEL: f1: 21 ; CHECK: memb(r{{[0-9]+}}+#0) -= #1 22 define void @f1() #0 { 23 b0: 24 %v0 = load i8, i8* @g0, align 1, !tbaa !0 25 %v1 = add i8 %v0, -1 26 store i8 %v1, i8* @g0, align 1, !tbaa !0 27 ret void 28 } 29 30 ; CHECK-LABEL: f2: 31 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 32 define void @f2() #0 { 33 b0: 34 %v0 = load i8, i8* @g0, align 1, !tbaa !0 35 %v1 = zext i8 %v0 to i32 36 %v2 = add nsw i32 %v1, 5 37 %v3 = trunc i32 %v2 to i8 38 store i8 %v3, i8* @g0, align 1, !tbaa !0 39 ret void 40 } 41 42 ; CHECK-LABEL: f3: 43 ; CHECK: memb(r{{[0-9]+}}+#0) -= #5 44 define void @f3() #0 { 45 b0: 46 %v0 = load i8, i8* @g0, align 1, !tbaa !0 47 %v1 = zext i8 %v0 to i32 48 %v2 = add nsw i32 %v1, 251 49 %v3 = trunc i32 %v2 to i8 50 store i8 %v3, i8* @g0, align 1, !tbaa !0 51 ret void 52 } 53 54 ; CHECK-LABEL: f4: 55 ; CHECK: memb(r{{[0-9]+}}+#0) -= #5 56 define void @f4() #0 { 57 b0: 58 %v0 = load i8, i8* @g0, align 1, !tbaa !0 59 %v1 = zext i8 %v0 to i32 60 %v2 = add nsw i32 %v1, 251 61 %v3 = trunc i32 %v2 to i8 62 store i8 %v3, i8* @g0, align 1, !tbaa !0 63 ret void 64 } 65 66 ; CHECK-LABEL: f5: 67 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 68 define void @f5() #0 { 69 b0: 70 %v0 = load i8, i8* @g0, align 1, !tbaa !0 71 %v1 = zext i8 %v0 to i32 72 %v2 = add nsw i32 %v1, 5 73 %v3 = trunc i32 %v2 to i8 74 store i8 %v3, i8* @g0, align 1, !tbaa !0 75 ret void 76 } 77 78 ; CHECK-LABEL: f6: 79 ; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} 80 define void @f6(i8 zeroext %a0) #0 { 81 b0: 82 %v0 = zext i8 %a0 to i32 83 %v1 = load i8, i8* @g0, align 1, !tbaa !0 84 %v2 = zext i8 %v1 to i32 85 %v3 = add nsw i32 %v2, %v0 86 %v4 = trunc i32 %v3 to i8 87 store i8 %v4, i8* @g0, align 1, !tbaa !0 88 ret void 89 } 90 91 ; CHECK-LABEL: f7: 92 ; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 93 define void @f7(i8 zeroext %a0) #0 { 94 b0: 95 %v0 = zext i8 %a0 to i32 96 %v1 = load i8, i8* @g0, align 1, !tbaa !0 97 %v2 = zext i8 %v1 to i32 98 %v3 = sub nsw i32 %v2, %v0 99 %v4 = trunc i32 %v3 to i8 100 store i8 %v4, i8* @g0, align 1, !tbaa !0 101 ret void 102 } 103 104 ; CHECK-LABEL: f8: 105 ; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 106 define void @f8(i8 zeroext %a0) #0 { 107 b0: 108 %v0 = load i8, i8* @g0, align 1, !tbaa !0 109 %v1 = or i8 %v0, %a0 110 store i8 %v1, i8* @g0, align 1, !tbaa !0 111 ret void 112 } 113 114 ; CHECK-LABEL: f9: 115 ; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 116 define void @f9(i8 zeroext %a0) #0 { 117 b0: 118 %v0 = load i8, i8* @g0, align 1, !tbaa !0 119 %v1 = and i8 %v0, %a0 120 store i8 %v1, i8* @g0, align 1, !tbaa !0 121 ret void 122 } 123 124 ; CHECK-LABEL: f10: 125 ; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) 126 define void @f10() #0 { 127 b0: 128 %v0 = load i8, i8* @g0, align 1, !tbaa !0 129 %v1 = zext i8 %v0 to i32 130 %v2 = and i32 %v1, 223 131 %v3 = trunc i32 %v2 to i8 132 store i8 %v3, i8* @g0, align 1, !tbaa !0 133 ret void 134 } 135 136 ; CHECK-LABEL: f11: 137 ; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) 138 define void @f11() #0 { 139 b0: 140 %v0 = load i8, i8* @g0, align 1, !tbaa !0 141 %v1 = zext i8 %v0 to i32 142 %v2 = or i32 %v1, 128 143 %v3 = trunc i32 %v2 to i8 144 store i8 %v3, i8* @g0, align 1, !tbaa !0 145 ret void 146 } 147 148 ; CHECK-LABEL: f12: 149 ; CHECK: memb(r{{[0-9]+}}+#0) += #1 150 define void @f12() #0 { 151 b0: 152 %v0 = load i8, i8* @g1, align 1, !tbaa !0 153 %v1 = add i8 %v0, 1 154 store i8 %v1, i8* @g1, align 1, !tbaa !0 155 ret void 156 } 157 158 ; CHECK-LABEL: f13: 159 ; CHECK: memb(r{{[0-9]+}}+#0) -= #1 160 define void @f13() #0 { 161 b0: 162 %v0 = load i8, i8* @g1, align 1, !tbaa !0 163 %v1 = add i8 %v0, -1 164 store i8 %v1, i8* @g1, align 1, !tbaa !0 165 ret void 166 } 167 168 ; CHECK-LABEL: f14: 169 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 170 define void @f14() #0 { 171 b0: 172 %v0 = load i8, i8* @g1, align 1, !tbaa !0 173 %v1 = zext i8 %v0 to i32 174 %v2 = add nsw i32 %v1, 5 175 %v3 = trunc i32 %v2 to i8 176 store i8 %v3, i8* @g1, align 1, !tbaa !0 177 ret void 178 } 179 180 ; CHECK-LABEL: f15: 181 ; CHECK: memb(r{{[0-9]+}}+#0) -= #5 182 define void @f15() #0 { 183 b0: 184 %v0 = load i8, i8* @g1, align 1, !tbaa !0 185 %v1 = zext i8 %v0 to i32 186 %v2 = add nsw i32 %v1, 251 187 %v3 = trunc i32 %v2 to i8 188 store i8 %v3, i8* @g1, align 1, !tbaa !0 189 ret void 190 } 191 192 ; CHECK-LABEL: f16: 193 ; CHECK: memb(r{{[0-9]+}}+#0) -= #5 194 define void @f16() #0 { 195 b0: 196 %v0 = load i8, i8* @g1, align 1, !tbaa !0 197 %v1 = zext i8 %v0 to i32 198 %v2 = add nsw i32 %v1, 251 199 %v3 = trunc i32 %v2 to i8 200 store i8 %v3, i8* @g1, align 1, !tbaa !0 201 ret void 202 } 203 204 ; CHECK-LABEL: f17: 205 ; CHECK: memb(r{{[0-9]+}}+#0) += #5 206 define void @f17() #0 { 207 b0: 208 %v0 = load i8, i8* @g1, align 1, !tbaa !0 209 %v1 = zext i8 %v0 to i32 210 %v2 = add nsw i32 %v1, 5 211 %v3 = trunc i32 %v2 to i8 212 store i8 %v3, i8* @g1, align 1, !tbaa !0 213 ret void 214 } 215 216 ; CHECK-LABEL: f18: 217 ; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} 218 define void @f18(i8 signext %a0) #0 { 219 b0: 220 %v0 = zext i8 %a0 to i32 221 %v1 = load i8, i8* @g1, align 1, !tbaa !0 222 %v2 = zext i8 %v1 to i32 223 %v3 = add nsw i32 %v2, %v0 224 %v4 = trunc i32 %v3 to i8 225 store i8 %v4, i8* @g1, align 1, !tbaa !0 226 ret void 227 } 228 229 ; CHECK-LABEL: f19: 230 ; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 231 define void @f19(i8 signext %a0) #0 { 232 b0: 233 %v0 = zext i8 %a0 to i32 234 %v1 = load i8, i8* @g1, align 1, !tbaa !0 235 %v2 = zext i8 %v1 to i32 236 %v3 = sub nsw i32 %v2, %v0 237 %v4 = trunc i32 %v3 to i8 238 store i8 %v4, i8* @g1, align 1, !tbaa !0 239 ret void 240 } 241 242 ; CHECK-LABEL: f20: 243 ; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 244 define void @f20(i8 signext %a0) #0 { 245 b0: 246 %v0 = load i8, i8* @g1, align 1, !tbaa !0 247 %v1 = or i8 %v0, %a0 248 store i8 %v1, i8* @g1, align 1, !tbaa !0 249 ret void 250 } 251 252 ; CHECK-LABEL: f21: 253 ; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 254 define void @f21(i8 signext %a0) #0 { 255 b0: 256 %v0 = load i8, i8* @g1, align 1, !tbaa !0 257 %v1 = and i8 %v0, %a0 258 store i8 %v1, i8* @g1, align 1, !tbaa !0 259 ret void 260 } 261 262 ; CHECK-LABEL: f22: 263 ; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) 264 define void @f22() #0 { 265 b0: 266 %v0 = load i8, i8* @g1, align 1, !tbaa !0 267 %v1 = zext i8 %v0 to i32 268 %v2 = and i32 %v1, 223 269 %v3 = trunc i32 %v2 to i8 270 store i8 %v3, i8* @g1, align 1, !tbaa !0 271 ret void 272 } 273 274 ; CHECK-LABEL: f23: 275 ; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) 276 define void @f23() #0 { 277 b0: 278 %v0 = load i8, i8* @g1, align 1, !tbaa !0 279 %v1 = zext i8 %v0 to i32 280 %v2 = or i32 %v1, 128 281 %v3 = trunc i32 %v2 to i8 282 store i8 %v3, i8* @g1, align 1, !tbaa !0 283 ret void 284 } 285 286 ; CHECK-LABEL: f24: 287 ; CHECK: memh(r{{[0-9]+}}+#0) += #1 288 define void @f24() #0 { 289 b0: 290 %v0 = load i16, i16* @g2, align 2, !tbaa !3 291 %v1 = add i16 %v0, 1 292 store i16 %v1, i16* @g2, align 2, !tbaa !3 293 ret void 294 } 295 296 ; CHECK-LABEL: f25: 297 ; CHECK: memh(r{{[0-9]+}}+#0) -= #1 298 define void @f25() #0 { 299 b0: 300 %v0 = load i16, i16* @g2, align 2, !tbaa !3 301 %v1 = add i16 %v0, -1 302 store i16 %v1, i16* @g2, align 2, !tbaa !3 303 ret void 304 } 305 306 ; CHECK-LABEL: f26: 307 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 308 define void @f26() #0 { 309 b0: 310 %v0 = load i16, i16* @g2, align 2, !tbaa !3 311 %v1 = zext i16 %v0 to i32 312 %v2 = add nsw i32 %v1, 5 313 %v3 = trunc i32 %v2 to i16 314 store i16 %v3, i16* @g2, align 2, !tbaa !3 315 ret void 316 } 317 318 ; CHECK-LABEL: f27: 319 ; CHECK: memh(r{{[0-9]+}}+#0) -= #5 320 define void @f27() #0 { 321 b0: 322 %v0 = load i16, i16* @g2, align 2, !tbaa !3 323 %v1 = zext i16 %v0 to i32 324 %v2 = add nsw i32 %v1, 65531 325 %v3 = trunc i32 %v2 to i16 326 store i16 %v3, i16* @g2, align 2, !tbaa !3 327 ret void 328 } 329 330 ; CHECK-LABEL: f28: 331 ; CHECK: memh(r{{[0-9]+}}+#0) -= #5 332 define void @f28() #0 { 333 b0: 334 %v0 = load i16, i16* @g2, align 2, !tbaa !3 335 %v1 = zext i16 %v0 to i32 336 %v2 = add nsw i32 %v1, 65531 337 %v3 = trunc i32 %v2 to i16 338 store i16 %v3, i16* @g2, align 2, !tbaa !3 339 ret void 340 } 341 342 ; CHECK-LABEL: f29: 343 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 344 define void @f29() #0 { 345 b0: 346 %v0 = load i16, i16* @g2, align 2, !tbaa !3 347 %v1 = zext i16 %v0 to i32 348 %v2 = add nsw i32 %v1, 5 349 %v3 = trunc i32 %v2 to i16 350 store i16 %v3, i16* @g2, align 2, !tbaa !3 351 ret void 352 } 353 354 ; CHECK-LABEL: f30: 355 ; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} 356 define void @f30(i16 zeroext %a0) #0 { 357 b0: 358 %v0 = zext i16 %a0 to i32 359 %v1 = load i16, i16* @g2, align 2, !tbaa !3 360 %v2 = zext i16 %v1 to i32 361 %v3 = add nsw i32 %v2, %v0 362 %v4 = trunc i32 %v3 to i16 363 store i16 %v4, i16* @g2, align 2, !tbaa !3 364 ret void 365 } 366 367 ; CHECK-LABEL: f31: 368 ; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 369 define void @f31(i16 zeroext %a0) #0 { 370 b0: 371 %v0 = zext i16 %a0 to i32 372 %v1 = load i16, i16* @g2, align 2, !tbaa !3 373 %v2 = zext i16 %v1 to i32 374 %v3 = sub nsw i32 %v2, %v0 375 %v4 = trunc i32 %v3 to i16 376 store i16 %v4, i16* @g2, align 2, !tbaa !3 377 ret void 378 } 379 380 ; CHECK-LABEL: f32: 381 ; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 382 define void @f32(i16 zeroext %a0) #0 { 383 b0: 384 %v0 = load i16, i16* @g2, align 2, !tbaa !3 385 %v1 = or i16 %v0, %a0 386 store i16 %v1, i16* @g2, align 2, !tbaa !3 387 ret void 388 } 389 390 ; CHECK-LABEL: f33: 391 ; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 392 define void @f33(i16 zeroext %a0) #0 { 393 b0: 394 %v0 = load i16, i16* @g2, align 2, !tbaa !3 395 %v1 = and i16 %v0, %a0 396 store i16 %v1, i16* @g2, align 2, !tbaa !3 397 ret void 398 } 399 400 ; CHECK-LABEL: f34: 401 ; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) 402 define void @f34() #0 { 403 b0: 404 %v0 = load i16, i16* @g2, align 2, !tbaa !3 405 %v1 = zext i16 %v0 to i32 406 %v2 = and i32 %v1, 65503 407 %v3 = trunc i32 %v2 to i16 408 store i16 %v3, i16* @g2, align 2, !tbaa !3 409 ret void 410 } 411 412 ; CHECK-LABEL: f35: 413 ; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) 414 define void @f35() #0 { 415 b0: 416 %v0 = load i16, i16* @g2, align 2, !tbaa !3 417 %v1 = zext i16 %v0 to i32 418 %v2 = or i32 %v1, 128 419 %v3 = trunc i32 %v2 to i16 420 store i16 %v3, i16* @g2, align 2, !tbaa !3 421 ret void 422 } 423 424 ; CHECK-LABEL: f36: 425 ; CHECK: memh(r{{[0-9]+}}+#0) += #1 426 define void @f36() #0 { 427 b0: 428 %v0 = load i16, i16* @g3, align 2, !tbaa !3 429 %v1 = add i16 %v0, 1 430 store i16 %v1, i16* @g3, align 2, !tbaa !3 431 ret void 432 } 433 434 ; CHECK-LABEL: f37: 435 ; CHECK: memh(r{{[0-9]+}}+#0) -= #1 436 define void @f37() #0 { 437 b0: 438 %v0 = load i16, i16* @g3, align 2, !tbaa !3 439 %v1 = add i16 %v0, -1 440 store i16 %v1, i16* @g3, align 2, !tbaa !3 441 ret void 442 } 443 444 ; CHECK-LABEL: f38: 445 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 446 define void @f38() #0 { 447 b0: 448 %v0 = load i16, i16* @g3, align 2, !tbaa !3 449 %v1 = zext i16 %v0 to i32 450 %v2 = add nsw i32 %v1, 5 451 %v3 = trunc i32 %v2 to i16 452 store i16 %v3, i16* @g3, align 2, !tbaa !3 453 ret void 454 } 455 456 ; CHECK-LABEL: f39: 457 ; CHECK: memh(r{{[0-9]+}}+#0) -= #5 458 define void @f39() #0 { 459 b0: 460 %v0 = load i16, i16* @g3, align 2, !tbaa !3 461 %v1 = zext i16 %v0 to i32 462 %v2 = add nsw i32 %v1, 65531 463 %v3 = trunc i32 %v2 to i16 464 store i16 %v3, i16* @g3, align 2, !tbaa !3 465 ret void 466 } 467 468 ; CHECK-LABEL: f40: 469 ; CHECK: memh(r{{[0-9]+}}+#0) -= #5 470 define void @f40() #0 { 471 b0: 472 %v0 = load i16, i16* @g3, align 2, !tbaa !3 473 %v1 = zext i16 %v0 to i32 474 %v2 = add nsw i32 %v1, 65531 475 %v3 = trunc i32 %v2 to i16 476 store i16 %v3, i16* @g3, align 2, !tbaa !3 477 ret void 478 } 479 480 ; CHECK-LABEL: f41 481 ; CHECK: memh(r{{[0-9]+}}+#0) += #5 482 define void @f41() #0 { 483 b0: 484 %v0 = load i16, i16* @g3, align 2, !tbaa !3 485 %v1 = zext i16 %v0 to i32 486 %v2 = add nsw i32 %v1, 5 487 %v3 = trunc i32 %v2 to i16 488 store i16 %v3, i16* @g3, align 2, !tbaa !3 489 ret void 490 } 491 492 ; CHECK-LABEL: f42 493 ; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} 494 define void @f42(i16 signext %a0) #0 { 495 b0: 496 %v0 = zext i16 %a0 to i32 497 %v1 = load i16, i16* @g3, align 2, !tbaa !3 498 %v2 = zext i16 %v1 to i32 499 %v3 = add nsw i32 %v2, %v0 500 %v4 = trunc i32 %v3 to i16 501 store i16 %v4, i16* @g3, align 2, !tbaa !3 502 ret void 503 } 504 505 ; CHECK-LABEL: f43 506 ; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 507 define void @f43(i16 signext %a0) #0 { 508 b0: 509 %v0 = zext i16 %a0 to i32 510 %v1 = load i16, i16* @g3, align 2, !tbaa !3 511 %v2 = zext i16 %v1 to i32 512 %v3 = sub nsw i32 %v2, %v0 513 %v4 = trunc i32 %v3 to i16 514 store i16 %v4, i16* @g3, align 2, !tbaa !3 515 ret void 516 } 517 518 ; CHECK-LABEL: f44 519 ; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 520 define void @f44(i16 signext %a0) #0 { 521 b0: 522 %v0 = load i16, i16* @g3, align 2, !tbaa !3 523 %v1 = or i16 %v0, %a0 524 store i16 %v1, i16* @g3, align 2, !tbaa !3 525 ret void 526 } 527 528 ; CHECK-LABEL: f45 529 ; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 530 define void @f45(i16 signext %a0) #0 { 531 b0: 532 %v0 = load i16, i16* @g3, align 2, !tbaa !3 533 %v1 = and i16 %v0, %a0 534 store i16 %v1, i16* @g3, align 2, !tbaa !3 535 ret void 536 } 537 538 ; CHECK-LABEL: f46 539 ; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) 540 define void @f46() #0 { 541 b0: 542 %v0 = load i16, i16* @g3, align 2, !tbaa !3 543 %v1 = zext i16 %v0 to i32 544 %v2 = and i32 %v1, 65503 545 %v3 = trunc i32 %v2 to i16 546 store i16 %v3, i16* @g3, align 2, !tbaa !3 547 ret void 548 } 549 550 ; CHECK-LABEL: f47 551 ; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) 552 define void @f47() #0 { 553 b0: 554 %v0 = load i16, i16* @g3, align 2, !tbaa !3 555 %v1 = zext i16 %v0 to i32 556 %v2 = or i32 %v1, 128 557 %v3 = trunc i32 %v2 to i16 558 store i16 %v3, i16* @g3, align 2, !tbaa !3 559 ret void 560 } 561 562 ; CHECK-LABEL: f48 563 ; CHECK: memw(r{{[0-9]+}}+#0) += #1 564 define void @f48() #0 { 565 b0: 566 %v0 = load i32, i32* @g4, align 4, !tbaa !5 567 %v1 = add nsw i32 %v0, 1 568 store i32 %v1, i32* @g4, align 4, !tbaa !5 569 ret void 570 } 571 572 ; CHECK-LABEL: f49 573 ; CHECK: memw(r{{[0-9]+}}+#0) -= #1 574 define void @f49() #0 { 575 b0: 576 %v0 = load i32, i32* @g4, align 4, !tbaa !5 577 %v1 = add nsw i32 %v0, -1 578 store i32 %v1, i32* @g4, align 4, !tbaa !5 579 ret void 580 } 581 582 ; CHECK-LABEL: f50 583 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 584 define void @f50() #0 { 585 b0: 586 %v0 = load i32, i32* @g4, align 4, !tbaa !5 587 %v1 = add nsw i32 %v0, 5 588 store i32 %v1, i32* @g4, align 4, !tbaa !5 589 ret void 590 } 591 592 ; CHECK-LABEL: f51 593 ; CHECK: memw(r{{[0-9]+}}+#0) -= #5 594 define void @f51() #0 { 595 b0: 596 %v0 = load i32, i32* @g4, align 4, !tbaa !5 597 %v1 = add nsw i32 %v0, -5 598 store i32 %v1, i32* @g4, align 4, !tbaa !5 599 ret void 600 } 601 602 ; CHECK-LABEL: f52 603 ; CHECK: memw(r{{[0-9]+}}+#0) -= #5 604 define void @f52() #0 { 605 b0: 606 %v0 = load i32, i32* @g4, align 4, !tbaa !5 607 %v1 = add nsw i32 %v0, -5 608 store i32 %v1, i32* @g4, align 4, !tbaa !5 609 ret void 610 } 611 612 ; CHECK-LABEL: f53 613 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 614 define void @f53() #0 { 615 b0: 616 %v0 = load i32, i32* @g4, align 4, !tbaa !5 617 %v1 = add nsw i32 %v0, 5 618 store i32 %v1, i32* @g4, align 4, !tbaa !5 619 ret void 620 } 621 622 ; CHECK-LABEL: f54 623 ; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} 624 define void @f54(i32 %a0) #0 { 625 b0: 626 %v0 = load i32, i32* @g4, align 4, !tbaa !5 627 %v1 = add i32 %v0, %a0 628 store i32 %v1, i32* @g4, align 4, !tbaa !5 629 ret void 630 } 631 632 ; CHECK-LABEL: f55 633 ; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 634 define void @f55(i32 %a0) #0 { 635 b0: 636 %v0 = load i32, i32* @g4, align 4, !tbaa !5 637 %v1 = sub i32 %v0, %a0 638 store i32 %v1, i32* @g4, align 4, !tbaa !5 639 ret void 640 } 641 642 ; CHECK-LABEL: f56 643 ; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 644 define void @f56(i32 %a0) #0 { 645 b0: 646 %v0 = load i32, i32* @g4, align 4, !tbaa !5 647 %v1 = or i32 %v0, %a0 648 store i32 %v1, i32* @g4, align 4, !tbaa !5 649 ret void 650 } 651 652 ; CHECK-LABEL: f57 653 ; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 654 define void @f57(i32 %a0) #0 { 655 b0: 656 %v0 = load i32, i32* @g4, align 4, !tbaa !5 657 %v1 = and i32 %v0, %a0 658 store i32 %v1, i32* @g4, align 4, !tbaa !5 659 ret void 660 } 661 662 ; CHECK-LABEL: f58 663 ; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) 664 define void @f58() #0 { 665 b0: 666 %v0 = load i32, i32* @g4, align 4, !tbaa !5 667 %v1 = and i32 %v0, -33 668 store i32 %v1, i32* @g4, align 4, !tbaa !5 669 ret void 670 } 671 672 ; CHECK-LABEL: f59 673 ; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) 674 define void @f59() #0 { 675 b0: 676 %v0 = load i32, i32* @g4, align 4, !tbaa !5 677 %v1 = or i32 %v0, 128 678 store i32 %v1, i32* @g4, align 4, !tbaa !5 679 ret void 680 } 681 682 ; CHECK-LABEL: f60 683 ; CHECK: memw(r{{[0-9]+}}+#0) += #1 684 define void @f60() #0 { 685 b0: 686 %v0 = load i32, i32* @g5, align 4, !tbaa !5 687 %v1 = add i32 %v0, 1 688 store i32 %v1, i32* @g5, align 4, !tbaa !5 689 ret void 690 } 691 692 ; CHECK-LABEL: f61 693 ; CHECK: memw(r{{[0-9]+}}+#0) -= #1 694 define void @f61() #0 { 695 b0: 696 %v0 = load i32, i32* @g5, align 4, !tbaa !5 697 %v1 = add i32 %v0, -1 698 store i32 %v1, i32* @g5, align 4, !tbaa !5 699 ret void 700 } 701 702 ; CHECK-LABEL: f62 703 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 704 define void @f62() #0 { 705 b0: 706 %v0 = load i32, i32* @g5, align 4, !tbaa !5 707 %v1 = add i32 %v0, 5 708 store i32 %v1, i32* @g5, align 4, !tbaa !5 709 ret void 710 } 711 712 ; CHECK-LABEL: f63 713 ; CHECK: memw(r{{[0-9]+}}+#0) -= #5 714 define void @f63() #0 { 715 b0: 716 %v0 = load i32, i32* @g5, align 4, !tbaa !5 717 %v1 = add i32 %v0, -5 718 store i32 %v1, i32* @g5, align 4, !tbaa !5 719 ret void 720 } 721 722 ; CHECK-LABEL: f64 723 ; CHECK: memw(r{{[0-9]+}}+#0) -= #5 724 define void @f64() #0 { 725 b0: 726 %v0 = load i32, i32* @g5, align 4, !tbaa !5 727 %v1 = add i32 %v0, -5 728 store i32 %v1, i32* @g5, align 4, !tbaa !5 729 ret void 730 } 731 732 ; CHECK-LABEL: f65 733 ; CHECK: memw(r{{[0-9]+}}+#0) += #5 734 define void @f65() #0 { 735 b0: 736 %v0 = load i32, i32* @g5, align 4, !tbaa !5 737 %v1 = add i32 %v0, 5 738 store i32 %v1, i32* @g5, align 4, !tbaa !5 739 ret void 740 } 741 742 ; CHECK-LABEL: f66: 743 ; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} 744 define void @f66(i32 %a0) #0 { 745 b0: 746 %v0 = load i32, i32* @g5, align 4, !tbaa !5 747 %v1 = add i32 %v0, %a0 748 store i32 %v1, i32* @g5, align 4, !tbaa !5 749 ret void 750 } 751 752 ; CHECK-LABEL: f67: 753 ; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} 754 define void @f67(i32 %a0) #0 { 755 b0: 756 %v0 = load i32, i32* @g5, align 4, !tbaa !5 757 %v1 = sub i32 %v0, %a0 758 store i32 %v1, i32* @g5, align 4, !tbaa !5 759 ret void 760 } 761 762 ; CHECK-LABEL: f68: 763 ; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} 764 define void @f68(i32 %a0) #0 { 765 b0: 766 %v0 = load i32, i32* @g5, align 4, !tbaa !5 767 %v1 = or i32 %v0, %a0 768 store i32 %v1, i32* @g5, align 4, !tbaa !5 769 ret void 770 } 771 772 ; CHECK-LABEL: f69: 773 ; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} 774 define void @f69(i32 %a0) #0 { 775 b0: 776 %v0 = load i32, i32* @g5, align 4, !tbaa !5 777 %v1 = and i32 %v0, %a0 778 store i32 %v1, i32* @g5, align 4, !tbaa !5 779 ret void 780 } 781 782 ; CHECK-LABEL: f70: 783 ; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) 784 define void @f70() #0 { 785 b0: 786 %v0 = load i32, i32* @g5, align 4, !tbaa !5 787 %v1 = and i32 %v0, -33 788 store i32 %v1, i32* @g5, align 4, !tbaa !5 789 ret void 790 } 791 792 ; CHECK-LABEL: f71: 793 ; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) 794 define void @f71() #0 { 795 b0: 796 %v0 = load i32, i32* @g5, align 4, !tbaa !5 797 %v1 = or i32 %v0, 128 798 store i32 %v1, i32* @g5, align 4, !tbaa !5 799 ret void 800 } 801 802 attributes #0 = { nounwind } 803 804 !0 = !{!1, !1, i64 0} 805 !1 = !{!"omnipotent char", !2} 806 !2 = !{!"Simple C/C++ TBAA"} 807 !3 = !{!4, !4, i64 0} 808 !4 = !{!"short", !1} 809 !5 = !{!6, !6, i64 0} 810 !6 = !{!"int", !1} 811
