1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; CHECK: r{{[0-9]+}}:{{[0-9]+}} ^= pmpyw(r{{[0-9]+}},r{{[0-9]+}}) 3 4 ; Function Attrs: nounwind 5 define i32 @f0(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 { 6 b0: 7 %v0 = alloca i32, align 4 8 %v1 = alloca i32, align 4 9 %v2 = alloca i32, align 4 10 %v3 = alloca i32, align 4 11 %v4 = alloca i64, align 8 12 %v5 = alloca i64, align 8 13 store i32 %a0, i32* %v0, align 4 14 store i32 %a1, i32* %v1, align 4 15 store i32 %a2, i32* %v2, align 4 16 store i32 %a3, i32* %v3, align 4 17 %v6 = load i32, i32* %v0, align 4 18 %v7 = load i32, i32* %v1, align 4 19 %v8 = call i64 @llvm.hexagon.M4.pmpyw(i32 %v6, i32 %v7) 20 store i64 %v8, i64* %v5, align 8 21 %v9 = load i64, i64* %v5, align 8 22 store i64 %v9, i64* %v4, align 8 23 %v10 = load i64, i64* %v5, align 8 24 %v11 = load i32, i32* %v3, align 4 25 %v12 = load i64, i64* %v5, align 8 26 %v13 = lshr i64 %v12, 32 27 %v14 = trunc i64 %v13 to i32 28 %v15 = call i64 @llvm.hexagon.M4.pmpyw.acc(i64 %v10, i32 %v11, i32 %v14) 29 store i64 %v15, i64* %v5, align 8 30 %v16 = load i64, i64* %v4, align 8 31 %v17 = load i64, i64* %v5, align 8 32 %v18 = lshr i64 %v17, 32 33 %v19 = trunc i64 %v18 to i32 34 %v20 = load i32, i32* %v2, align 4 35 %v21 = call i64 @llvm.hexagon.M4.pmpyw.acc(i64 %v16, i32 %v19, i32 %v20) 36 store i64 %v21, i64* %v4, align 8 37 %v22 = load i64, i64* %v4, align 8 38 %v23 = trunc i64 %v22 to i32 39 ret i32 %v23 40 } 41 42 ; Function Attrs: nounwind readnone 43 declare i64 @llvm.hexagon.M4.pmpyw(i32, i32) #1 44 45 ; Function Attrs: nounwind readnone 46 declare i64 @llvm.hexagon.M4.pmpyw.acc(i64, i32, i32) #1 47 48 attributes #0 = { nounwind } 49 attributes #1 = { nounwind readnone } 50
