1 ; RUN: llc -march=hexagon -O2 < %s 2 ; REQUIRES: asserts 3 ; Check for successful compilation. 4 5 target triple = "hexagon" 6 7 %s.0 = type { [1 x i32] } 8 %s.1 = type { %s.2, i8, %s.6 } 9 %s.2 = type { %s.3 } 10 %s.3 = type { %s.4 } 11 %s.4 = type { %s.5 } 12 %s.5 = type { i32 } 13 %s.6 = type { %s.6*, %s.6* } 14 15 @g0 = external constant %s.0* 16 @g1 = external global i32 17 @g2 = internal global %s.1 zeroinitializer, section ".data..percpu", align 4 18 @g3 = external global [3 x i32] 19 @g4 = private unnamed_addr constant [29 x i8] c"BUG: failure at %s:%d/%s()!\0A\00", align 1 20 @g5 = private unnamed_addr constant [22 x i8] c"kernel/stop_machine.c\00", align 1 21 @g6 = private unnamed_addr constant [14 x i8] c"cpu_stop_init\00", align 1 22 @g7 = private unnamed_addr constant [5 x i8] c"BUG!\00", align 1 23 24 ; Function Attrs: nounwind 25 define internal i32 @f0() #0 section ".init.text" { 26 b0: 27 %v0 = alloca i32, align 4 28 %v1 = load %s.0*, %s.0** @g0, align 4, !tbaa !0 29 %v2 = getelementptr inbounds %s.0, %s.0* %v1, i32 0, i32 0, i32 0 30 %v3 = tail call i32 @f1(i32* %v2, i32 3, i32 0) #0 31 %v4 = load i32, i32* @g1, align 4, !tbaa !4 32 %v5 = icmp ult i32 %v3, %v4 33 br i1 %v5, label %b1, label %b4 34 35 b1: ; preds = %b0 36 br label %b2 37 38 b2: ; preds = %b2, %b1 39 %v6 = phi i32 [ %v18, %b2 ], [ %v3, %b1 ] 40 %v7 = tail call i32 asm "", "=r,0"(%s.1* @g2) #0, !srcloc !6 41 %v8 = getelementptr inbounds [3 x i32], [3 x i32]* @g3, i32 0, i32 %v6 42 %v9 = load i32, i32* %v8, align 4, !tbaa !7 43 %v10 = add i32 %v9, %v7 44 %v11 = inttoptr i32 %v10 to %s.1* 45 store volatile i32 0, i32* %v0, align 4 46 %v12 = getelementptr inbounds %s.1, %s.1* %v11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 47 %v13 = load volatile i32, i32* %v0, align 4 48 store volatile i32 %v13, i32* %v12, align 4 49 %v14 = getelementptr inbounds %s.1, %s.1* %v11, i32 0, i32 2 50 %v15 = getelementptr inbounds %s.6, %s.6* %v14, i32 0, i32 0 51 store %s.6* %v14, %s.6** %v15, align 4, !tbaa !9 52 %v16 = getelementptr inbounds %s.1, %s.1* %v11, i32 0, i32 2, i32 1 53 store %s.6* %v14, %s.6** %v16, align 4, !tbaa !11 54 %v17 = add i32 %v6, 1 55 %v18 = tail call i32 @f1(i32* %v2, i32 3, i32 %v17) #0 56 %v19 = load i32, i32* @g1, align 4, !tbaa !4 57 %v20 = icmp ult i32 %v18, %v19 58 br i1 %v20, label %b2, label %b3 59 60 b3: ; preds = %b2 61 br label %b4 62 63 b4: ; preds = %b3, %b0 64 %v21 = tail call i32 @f2() #0 65 %v22 = icmp eq i32 %v21, 0 66 br i1 %v22, label %b6, label %b5, !prof !12 67 68 b5: ; preds = %b4 69 %v23 = tail call i32 (i8*, ...) @f3(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @g4, i32 0, i32 0), i8* getelementptr inbounds ([22 x i8], [22 x i8]* @g5, i32 0, i32 0), i32 354, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @g6, i32 0, i32 0)) #0 70 tail call void (i8*, ...) @f4(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @g7, i32 0, i32 0)) #1 71 unreachable 72 73 b6: ; preds = %b4 74 ret i32 0 75 } 76 77 ; Function Attrs: nounwind 78 declare i32 @f1(i32*, i32, i32) #0 79 80 ; Function Attrs: nounwind 81 declare i32 @f2() #0 82 83 ; Function Attrs: nounwind 84 declare i32 @f3(i8*, ...) #0 85 86 ; Function Attrs: noreturn 87 declare void @f4(i8*, ...) #1 88 89 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 90 attributes #1 = { noreturn } 91 92 !0 = !{!1, !1, i64 0} 93 !1 = !{!"any pointer", !2, i64 0} 94 !2 = !{!"omnipotent char", !3, i64 0} 95 !3 = !{!"Simple C/C++ TBAA"} 96 !4 = !{!5, !5, i64 0} 97 !5 = !{!"int", !2, i64 0} 98 !6 = !{i32 521672} 99 !7 = !{!8, !8, i64 0} 100 !8 = !{!"long", !2, i64 0} 101 !9 = !{!10, !1, i64 0} 102 !10 = !{!"list_head", !1, i64 0, !1, i64 4} 103 !11 = !{!10, !1, i64 4} 104 !12 = !{!"branch_weights", i32 64, i32 4} 105
