1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 4 ; After a copy R20 = R29, RDF copy propagation attempted to replace R20 with 5 ; R29. R29 did not have a reaching def at that point (which isn't unusual), 6 ; but copy propagation tried to link the new use of R29 to the presumed 7 ; reaching def (which was null), causing a crash. 8 9 target triple = "hexagon" 10 11 @g0 = external unnamed_addr global i1, align 4 12 13 ; Function Attrs: nounwind 14 declare i8* @llvm.stacksave() #0 15 16 ; Function Attrs: nounwind 17 declare void @llvm.stackrestore(i8*) #0 18 19 ; Function Attrs: norecurse nounwind 20 declare fastcc void @f0(i16 signext, i16 signext, i16 signext, i16* nocapture readonly, i16 signext, i16* nocapture) unnamed_addr #1 21 22 ; Function Attrs: norecurse nounwind 23 declare fastcc signext i16 @f1(i16 signext, i16 signext) unnamed_addr #1 24 25 ; Function Attrs: norecurse nounwind 26 define fastcc i32 @f2(i16* nocapture readonly %a0, i16 signext %a1, i16 signext %a2, i16* nocapture readonly %a3, i16 signext %a4, i16* nocapture readonly %a51, i16* nocapture %a6) unnamed_addr #1 { 27 b0: 28 %v0 = tail call i8* @llvm.stacksave() 29 %v1 = tail call fastcc signext i16 @f1(i16 signext %a2, i16 signext %a1) 30 br i1 undef, label %b7, label %b1 31 32 b1: ; preds = %b0 33 br i1 undef, label %b3, label %b2 34 35 b2: ; preds = %b1 36 br i1 undef, label %b4, label %b8 37 38 b3: ; preds = %b1 39 br i1 undef, label %b5, label %b8 40 41 b4: ; preds = %b4, %b2 42 br i1 undef, label %b4, label %b6, !llvm.loop !2 43 44 b5: ; preds = %b5, %b3 45 %v2 = phi i16 [ %v3, %b5 ], [ 0, %b3 ] 46 %v3 = add i16 %v2, 1 47 %v4 = icmp sgt i32 0, -1073741825 48 br i1 %v4, label %b5, label %b6 49 50 b6: ; preds = %b5, %b4 51 %v5 = phi i16 [ %v3, %b5 ], [ undef, %b4 ] 52 br label %b7 53 54 b7: ; preds = %b6, %b0 55 %v6 = phi i16 [ %v5, %b6 ], [ 0, %b0 ] 56 br i1 undef, label %b9, label %b8 57 58 b8: ; preds = %b7, %b3, %b2 59 %v7 = or i32 0, undef 60 br label %b9 61 62 b9: ; preds = %b8, %b7 63 %v8 = phi i16 [ 0, %b8 ], [ %v6, %b7 ] 64 %v9 = phi i32 [ %v7, %b8 ], [ 0, %b7 ] 65 %v10 = load i16, i16* undef, align 2, !tbaa !4 66 %v11 = sext i16 %v10 to i32 67 %v12 = zext i16 %v10 to i32 68 br i1 undef, label %b10, label %b11 69 70 b10: ; preds = %b9 71 store i1 true, i1* @g0, align 4 72 br label %b11 73 74 b11: ; preds = %b10, %b9 75 %v13 = load i16, i16* undef, align 2, !tbaa !4 76 %v14 = sext i16 %v13 to i32 77 %v15 = shl nuw i32 %v12, 16 78 %v16 = and i32 %v9, 65535 79 %v17 = mul nsw i32 %v11, %v16 80 %v18 = sitofp i32 %v15 to double 81 %v19 = fsub double %v18, undef 82 %v20 = sub nsw i32 %v15, %v17 83 %v21 = fptosi double %v19 to i32 84 %v22 = select i1 undef, i32 %v21, i32 %v20 85 %v23 = mul nsw i32 %v14, %v16 86 %v24 = add nsw i32 %v23, %v22 87 %v25 = add nsw i32 %v24, 32768 88 %v26 = lshr i32 %v25, 16 89 %v27 = xor i1 undef, true 90 %v28 = and i1 %v27, undef 91 br i1 %v28, label %b12, label %b13 92 93 b12: ; preds = %b11 94 store i1 true, i1* @g0, align 4 95 br label %b13 96 97 b13: ; preds = %b12, %b11 98 br i1 undef, label %b14, label %b24 99 100 b14: ; preds = %b13 101 br label %b15 102 103 b15: ; preds = %b23, %b14 104 br i1 undef, label %b16, label %b17 105 106 b16: ; preds = %b15 107 br label %b19 108 109 b17: ; preds = %b15 110 %v29 = trunc i32 %v26 to i16 111 %v30 = icmp eq i16 %v29, -32768 112 %v31 = and i1 undef, %v30 113 br i1 %v31, label %b18, label %b19 114 115 b18: ; preds = %b17 116 store i1 true, i1* @g0, align 4 117 br label %b20 118 119 b19: ; preds = %b17, %b16 120 br label %b20 121 122 b20: ; preds = %b19, %b18 123 %v32 = phi i32 [ 2147483647, %b18 ], [ 0, %b19 ] 124 %v33 = icmp eq i16 %v8, 32767 125 br i1 %v33, label %b21, label %b22 126 127 b21: ; preds = %b20 128 store i1 true, i1* @g0, align 4 129 br label %b23 130 131 b22: ; preds = %b20 132 br label %b23 133 134 b23: ; preds = %b22, %b21 135 %v34 = add nsw i32 %v32, 32768 136 %v35 = lshr i32 %v34, 16 137 %v36 = trunc i32 %v35 to i16 138 store i16 %v36, i16* undef, align 2, !tbaa !4 139 br i1 undef, label %b24, label %b15 140 141 b24: ; preds = %b23, %b13 142 call fastcc void @f0(i16 signext undef, i16 signext %a1, i16 signext %a2, i16* %a3, i16 signext %a4, i16* %a6) 143 call void @llvm.stackrestore(i8* %v0) 144 ret i32 undef 145 } 146 147 attributes #0 = { nounwind } 148 attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 149 150 !llvm.module.flags = !{!0} 151 152 !0 = !{i32 6, !"Target Features", !1} 153 !1 = !{!"+hvx,+hvx-length64b"} 154 !2 = distinct !{!2, !3} 155 !3 = !{!"llvm.loop.threadify", i32 43789156} 156 !4 = !{!5, !5, i64 0} 157 !5 = !{!"short", !6, i64 0} 158 !6 = !{!"omnipotent char", !7, i64 0} 159 !7 = !{!"Simple C++ TBAA"} 160
