1 ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s 2 3 ; Check for sane output. 4 ; CHECK: vmpyweh 5 6 target triple = "hexagon" 7 8 declare i32 @llvm.hexagon.S2.clb(i32) #0 9 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #0 10 declare i32 @llvm.hexagon.S2.vrndpackwh(i64) #0 11 declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64) #0 12 13 define i64 @fred(i32 %a0, i32 %a1) local_unnamed_addr #1 { 14 b2: 15 br i1 undef, label %b15, label %b3 16 17 b3: ; preds = %b2 18 %v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a1) #0 19 %v5 = add nsw i32 %v4, -32 20 %v6 = zext i32 %v5 to i64 21 %v7 = shl nuw i64 %v6, 32 22 %v8 = or i64 %v7, 0 23 %v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 0) 24 %v10 = tail call i32 @llvm.hexagon.S2.vrndpackwh(i64 %v8) 25 %v11 = sext i32 %v9 to i64 26 %v12 = sext i32 %v10 to i64 27 %v13 = tail call i64 @llvm.hexagon.M2.mmpyl.s1(i64 %v11, i64 %v12) 28 %v14 = and i64 %v13, 4294967295 29 br label %b15 30 31 b15: ; preds = %b3, %b2 32 %v16 = phi i64 [ %v14, %b3 ], [ 0, %b2 ] 33 %v17 = or i64 0, %v16 34 ret i64 %v17 35 } 36 37 attributes #0 = { nounwind readnone } 38 attributes #1 = { nounwind "target-cpu"="hexagonv55" } 39
