1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 4 ; Test that the register scavenger does not assert because a spill slot 5 ; was not found. The bug is that the Hexagon spill code was not allocating 6 ; the spill slot because the function that returns true, which indicates 7 ; the code changed when a spill is inserted, was not always returning true. 8 9 ; Function Attrs: nounwind 10 define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8* noalias nocapture %a4, i32 %a5) #0 { 11 b0: 12 %v0 = sub i32 0, %a1 13 %v1 = getelementptr inbounds i8, i8* %a0, i32 %v0 14 %v2 = getelementptr inbounds i8, i8* %a0, i32 %a1 15 %v3 = mul nsw i32 %a1, 2 16 %v4 = getelementptr inbounds i8, i8* %a0, i32 %v3 17 %v5 = bitcast i8* %a4 to <16 x i32>* 18 %v6 = getelementptr inbounds i8, i8* %a4, i32 %a5 19 %v7 = bitcast i8* %v6 to <16 x i32>* 20 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vd0() 21 %v9 = load <16 x i32>, <16 x i32>* undef, align 64 22 %v10 = or i64 undef, 0 23 %v11 = trunc i64 %v10 to i32 24 %v12 = load i8, i8* undef, align 1 25 %v13 = zext i8 %v12 to i64 26 %v14 = shl nuw nsw i64 %v13, 8 27 %v15 = or i64 0, %v14 28 %v16 = trunc i64 %v15 to i32 29 %v17 = load i8, i8* undef, align 1 30 %v18 = zext i8 %v17 to i64 31 %v19 = or i64 0, %v18 32 %v20 = or i64 %v19, 0 33 %v21 = or i64 %v20, 0 34 %v22 = trunc i64 %v21 to i32 35 %v23 = load i8, i8* undef, align 1 36 %v24 = zext i8 %v23 to i64 37 %v25 = shl nuw nsw i64 %v24, 8 38 %v26 = or i64 undef, %v25 39 %v27 = trunc i64 %v26 to i32 40 %v28 = icmp sgt i32 %a2, 64 41 br i1 %v28, label %b1, label %b6 42 43 b1: ; preds = %b0 44 %v29 = getelementptr inbounds i8, i8* %v4, i32 64 45 %v30 = bitcast i8* %v29 to <16 x i32>* 46 %v31 = getelementptr inbounds i8, i8* %v2, i32 64 47 %v32 = bitcast i8* %v31 to <16 x i32>* 48 %v33 = getelementptr inbounds i8, i8* %a0, i32 64 49 %v34 = bitcast i8* %v33 to <16 x i32>* 50 %v35 = getelementptr inbounds i8, i8* %v1, i32 64 51 %v36 = bitcast i8* %v35 to <16 x i32>* 52 %v37 = add i32 0, 64 53 %v38 = getelementptr i8, i8* %a4, i32 %v37 54 %v39 = add i32 %a2, -65 55 %v40 = lshr i32 %v39, 6 56 %v41 = add nuw nsw i32 %v40, 1 57 %v42 = and i32 %v41, 3 58 %v43 = icmp eq i32 %v42, 0 59 br i1 undef, label %b2, label %b4 60 61 b2: ; preds = %b2, %b1 62 %v44 = phi i32 [ %v144, %b2 ], [ %a2, %b1 ] 63 %v45 = phi <16 x i32> [ %v101, %b2 ], [ %v8, %b1 ] 64 %v46 = phi <16 x i32> [ %v113, %b2 ], [ undef, %b1 ] 65 %v47 = phi <16 x i32> [ %v102, %b2 ], [ %v8, %b1 ] 66 %v48 = phi <16 x i32> [ %v118, %b2 ], [ undef, %b1 ] 67 %v49 = phi <16 x i32>* [ %v112, %b2 ], [ %v36, %b1 ] 68 %v50 = phi <16 x i32>* [ %v114, %b2 ], [ %v34, %b1 ] 69 %v51 = phi <16 x i32>* [ %v116, %b2 ], [ %v32, %b1 ] 70 %v52 = phi <16 x i32>* [ undef, %b2 ], [ %v30, %b1 ] 71 %v53 = phi <16 x i32>* [ %v139, %b2 ], [ %v5, %b1 ] 72 %v54 = phi <16 x i32>* [ %v143, %b2 ], [ %v7, %b1 ] 73 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v46, <16 x i32> %v45, i32 1) 74 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v47, i32 1) 75 %v57 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 1 76 %v58 = load <16 x i32>, <16 x i32>* %v49, align 64 77 %v59 = getelementptr inbounds <16 x i32>, <16 x i32>* %v50, i32 1 78 %v60 = load <16 x i32>, <16 x i32>* %v50, align 64 79 %v61 = load <16 x i32>, <16 x i32>* %v51, align 64 80 %v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v58, <16 x i32> %v46, i32 1) 81 %v63 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v60, <16 x i32> undef, i32 1) 82 %v64 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v61, <16 x i32> undef, i32 1) 83 %v65 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> %v48, i32 1) 84 %v66 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v55) 85 %v67 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v63, <16 x i32> %v56) 86 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v66, i32 %v11) 87 %v69 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> undef) 88 %v70 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v68, <32 x i32> %v67, i32 %v16) 89 %v71 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v63) 90 %v72 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v70, <32 x i32> %v71, i32 %v22) 91 %v73 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v72, <32 x i32> %v69, i32 0) 92 %v74 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v73, <16 x i32> %v64, i32 %v27) 93 %v75 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> zeroinitializer, <16 x i32> %v65, i32 %v27) 94 %v76 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v74) 95 %v77 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v76, <16 x i32> undef, i32 %a3) 96 %v78 = getelementptr inbounds <16 x i32>, <16 x i32>* %v53, i32 1 97 store <16 x i32> %v77, <16 x i32>* %v53, align 64 98 %v79 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v75) 99 %v80 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v79, <16 x i32> undef, i32 %a3) 100 %v81 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 1 101 store <16 x i32> %v80, <16 x i32>* %v54, align 64 102 %v82 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 2 103 %v83 = load <16 x i32>, <16 x i32>* %v57, align 64 104 %v84 = getelementptr inbounds <16 x i32>, <16 x i32>* %v50, i32 2 105 %v85 = load <16 x i32>, <16 x i32>* %v59, align 64 106 %v86 = load <16 x i32>, <16 x i32>* undef, align 64 107 %v87 = load <16 x i32>, <16 x i32>* null, align 64 108 %v88 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v83, <16 x i32> %v58, i32 1) 109 %v89 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v85, <16 x i32> %v60, i32 1) 110 %v90 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v86, <16 x i32> %v61, i32 1) 111 %v91 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v90, <16 x i32> undef) 112 %v92 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> undef, <32 x i32> undef, i32 %v16) 113 %v93 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v88, <16 x i32> %v89) 114 %v94 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v92, <32 x i32> %v93, i32 %v22) 115 %v95 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v94, <32 x i32> %v91, i32 0) 116 %v96 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v95, <16 x i32> %v90, i32 %v27) 117 %v97 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v96) 118 %v98 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v97, <16 x i32> undef, i32 %a3) 119 store <16 x i32> %v98, <16 x i32>* %v78, align 64 120 %v99 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 2 121 store <16 x i32> undef, <16 x i32>* %v81, align 64 122 %v100 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 3 123 %v101 = load <16 x i32>, <16 x i32>* %v82, align 64 124 %v102 = load <16 x i32>, <16 x i32>* %v84, align 64 125 %v103 = getelementptr inbounds <16 x i32>, <16 x i32>* %v51, i32 3 126 %v104 = load <16 x i32>, <16 x i32>* null, align 64 127 %v105 = getelementptr inbounds <16 x i32>, <16 x i32>* %v52, i32 3 128 %v106 = load <16 x i32>, <16 x i32>* undef, align 64 129 %v107 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> undef, i32 %a3) 130 store <16 x i32> %v107, <16 x i32>* undef, align 64 131 %v108 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> undef, i32 %a3) 132 %v109 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 3 133 store <16 x i32> %v108, <16 x i32>* %v99, align 64 134 %v110 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v104, <16 x i32> %v86, i32 1) 135 %v111 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v106, <16 x i32> %v87, i32 1) 136 %v112 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 4 137 %v113 = load <16 x i32>, <16 x i32>* %v100, align 64 138 %v114 = getelementptr inbounds <16 x i32>, <16 x i32>* %v50, i32 4 139 %v115 = load <16 x i32>, <16 x i32>* undef, align 64 140 %v116 = getelementptr inbounds <16 x i32>, <16 x i32>* %v51, i32 4 141 %v117 = load <16 x i32>, <16 x i32>* %v103, align 64 142 %v118 = load <16 x i32>, <16 x i32>* %v105, align 64 143 %v119 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v113, <16 x i32> %v101, i32 1) 144 %v120 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v115, <16 x i32> %v102, i32 1) 145 %v121 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v117, <16 x i32> %v104, i32 1) 146 %v122 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v118, <16 x i32> %v106, i32 1) 147 %v123 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v119, <16 x i32> undef) 148 %v124 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v120, <16 x i32> undef) 149 %v125 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v123, i32 %v11) 150 %v126 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v124, i32 %v11) 151 %v127 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v121, <16 x i32> %v110) 152 %v128 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v125, <32 x i32> %v124, i32 %v16) 153 %v129 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v126, <32 x i32> %v127, i32 %v16) 154 %v130 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v128, <32 x i32> undef, i32 %v22) 155 %v131 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v129, <32 x i32> undef, i32 %v22) 156 %v132 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v122, <16 x i32> %v111) 157 %v133 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v130, <32 x i32> %v127, i32 0) 158 %v134 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v131, <32 x i32> %v132, i32 0) 159 %v135 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v133, <16 x i32> %v121, i32 %v27) 160 %v136 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v134, <16 x i32> %v122, i32 %v27) 161 %v137 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v135) 162 %v138 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v137, <16 x i32> undef, i32 %a3) 163 %v139 = getelementptr inbounds <16 x i32>, <16 x i32>* %v53, i32 4 164 store <16 x i32> %v138, <16 x i32>* undef, align 64 165 %v140 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v136) 166 %v141 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v136) 167 %v142 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v140, <16 x i32> %v141, i32 %a3) 168 %v143 = getelementptr inbounds <16 x i32>, <16 x i32>* %v54, i32 4 169 store <16 x i32> %v142, <16 x i32>* %v109, align 64 170 %v144 = add nsw i32 %v44, -256 171 %v145 = icmp sgt i32 %v144, 256 172 br i1 %v145, label %b2, label %b3 173 174 b3: ; preds = %b2 175 %v146 = phi <16 x i32>* [ %v116, %b2 ] 176 %v147 = phi <16 x i32>* [ %v114, %b2 ] 177 %v148 = phi <16 x i32>* [ %v112, %b2 ] 178 br i1 %v43, label %b5, label %b4 179 180 b4: ; preds = %b3, %b1 181 %v149 = phi <16 x i32> [ %v9, %b1 ], [ undef, %b3 ] 182 %v150 = phi <16 x i32>* [ %v36, %b1 ], [ %v148, %b3 ] 183 %v151 = phi <16 x i32>* [ %v34, %b1 ], [ %v147, %b3 ] 184 %v152 = phi <16 x i32>* [ %v32, %b1 ], [ %v146, %b3 ] 185 %v153 = phi <16 x i32>* [ %v5, %b1 ], [ undef, %b3 ] 186 %v154 = load <16 x i32>, <16 x i32>* %v150, align 64 187 %v155 = load <16 x i32>, <16 x i32>* %v151, align 64 188 %v156 = load <16 x i32>, <16 x i32>* %v152, align 64 189 %v157 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v154, <16 x i32> undef, i32 1) 190 %v158 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v155, <16 x i32> undef, i32 1) 191 %v159 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v156, <16 x i32> %v149, i32 1) 192 %v160 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v157, <16 x i32> %v158) 193 %v161 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v160, i32 %v22) 194 %v162 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v161, <32 x i32> undef, i32 0) 195 %v163 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v162, <16 x i32> %v159, i32 %v27) 196 %v164 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v163) 197 %v165 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v164, <16 x i32> undef, i32 %a3) 198 store <16 x i32> %v165, <16 x i32>* %v153, align 64 199 unreachable 200 201 b5: ; preds = %b3 202 %v166 = bitcast i8* %v38 to <16 x i32>* 203 br label %b6 204 205 b6: ; preds = %b5, %b0 206 %v167 = phi <16 x i32> [ %v8, %b0 ], [ undef, %b5 ] 207 %v168 = phi <16 x i32>* [ %v5, %b0 ], [ %v166, %b5 ] 208 %v169 = phi <16 x i32>* [ %v7, %b0 ], [ undef, %b5 ] 209 %v170 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v167, i32 1) 210 %v171 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> undef, i32 1) 211 %v172 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v170) 212 %v173 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v171) 213 %v174 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v171, <16 x i32> undef) 214 %v175 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v173, i32 %v22) 215 %v176 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v174, i32 %v22) 216 %v177 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v175, <32 x i32> %v172, i32 0) 217 %v178 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v176, <32 x i32> undef, i32 0) 218 %v179 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v177, <16 x i32> undef, i32 %v27) 219 %v180 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v178, <16 x i32> undef, i32 %v27) 220 %v181 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v179) 221 %v182 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v181, i32 %a3) 222 store <16 x i32> %v182, <16 x i32>* %v168, align 64 223 %v183 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v180) 224 %v184 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v183, i32 %a3) 225 store <16 x i32> %v184, <16 x i32>* %v169, align 64 226 ret void 227 } 228 229 ; Function Attrs: nounwind readnone 230 declare <16 x i32> @llvm.hexagon.V6.vd0() #1 231 232 ; Function Attrs: nounwind readnone 233 declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1 234 235 ; Function Attrs: nounwind readnone 236 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 237 238 ; Function Attrs: nounwind readnone 239 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 240 241 ; Function Attrs: nounwind readnone 242 declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32>, i32) #1 243 244 ; Function Attrs: nounwind readnone 245 declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #1 246 247 ; Function Attrs: nounwind readnone 248 declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1 249 250 ; Function Attrs: nounwind readnone 251 declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #1 252 253 ; Function Attrs: nounwind readnone 254 declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #1 255 256 ; Function Attrs: nounwind readnone 257 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 258 259 ; Function Attrs: nounwind readnone 260 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 261 262 attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" } 263 attributes #1 = { nounwind readnone } 264
