1 ; RUN: llc -O3 -march=hexagon < %s | FileCheck %s 2 ; CHECK: v{{[0-9]+}}.w = vadd 3 4 target triple = "hexagon" 5 6 ; Function Attrs: nounwind readnone 7 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0 8 9 ; Function Attrs: nounwind readnone 10 declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #0 11 12 ; Function Attrs: nounwind readnone 13 declare <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32>, <16 x i32>) #0 14 15 ; Function Attrs: nounwind readnone 16 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0 17 18 ; Function Attrs: nounwind readnone 19 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #0 20 21 ; Function Attrs: nounwind 22 define void @f0(i16* noalias nocapture %a0, i32* noalias nocapture readonly %a1, i32 %a2, i8* noalias nocapture readonly %a3) #1 { 23 b0: 24 %v0 = add nsw i32 %a2, 63 25 %v1 = ashr i32 %v0, 6 26 %v2 = bitcast i16* %a0 to <16 x i32>* 27 %v3 = bitcast i8* %a3 to <16 x i32>* 28 %v4 = getelementptr inbounds i32, i32* %a1, i32 32 29 %v5 = bitcast i32* %v4 to <16 x i32>* 30 %v6 = load <16 x i32>, <16 x i32>* %v5, align 64, !tbaa !0 31 %v7 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 32768) 32 %v8 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2147450879) 33 %v9 = icmp sgt i32 %v1, 0 34 br i1 %v9, label %b1, label %b4 35 36 b1: ; preds = %b0 37 %v10 = bitcast i32* %a1 to <16 x i32>* 38 %v11 = load <16 x i32>, <16 x i32>* %v10, align 64, !tbaa !0 39 %v12 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v6, <16 x i32> %v11, i32 2) 40 %v13 = getelementptr inbounds i32, i32* %a1, i32 48 41 %v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v12, <16 x i32> undef) 42 %v15 = bitcast i32* %v13 to <16 x i32>* 43 br i1 undef, label %b2, label %b3 44 45 b2: ; preds = %b1 46 %v16 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 1 47 %v17 = load <16 x i32>, <16 x i32>* %v16, align 64, !tbaa !0 48 %v18 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v17, <16 x i32> %v6, i32 4) 49 %v19 = load <16 x i32>, <16 x i32>* %v15, align 64, !tbaa !0 50 %v20 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 2 51 %v21 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v18, <16 x i32> %v19) 52 %v22 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v21, <16 x i32> %v14, i32 4) 53 %v23 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v21, <16 x i32> %v14, i32 8) 54 %v24 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v21, <16 x i32> %v14, i32 12) 55 %v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v14, <16 x i32> %v22) 56 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v25, <16 x i32> %v23) 57 %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v26, <16 x i32> %v24) 58 %v28 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v19, <16 x i32> undef, i32 16) 59 %v29 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v27, <16 x i32> %v11) 60 %v30 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v27, <16 x i32> %v28) 61 %v31 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v29, i32 53019433) 62 %v32 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v30, i32 53019433) 63 %v33 = load <16 x i32>, <16 x i32>* %v3, align 64, !tbaa !0 64 %v34 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> %v33) 65 %v35 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> %v34, <16 x i32> %v34) 66 %v36 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v32, <16 x i32> %v31) 67 store <16 x i32> %v36, <16 x i32>* %v2, align 64, !tbaa !0 68 %v37 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 3 69 %v38 = load <16 x i32>, <16 x i32>* %v37, align 64, !tbaa !0 70 %v39 = load <16 x i32>, <16 x i32>* %v20, align 64, !tbaa !0 71 %v40 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 4 72 %v41 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> undef, <16 x i32> %v39) 73 %v42 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v41, <16 x i32> %v21, i32 4) 74 %v43 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v41, <16 x i32> %v21, i32 8) 75 %v44 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v41, <16 x i32> %v21, i32 12) 76 %v45 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v21, <16 x i32> %v42) 77 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v45, <16 x i32> %v43) 78 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v46, <16 x i32> %v44) 79 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v47, <16 x i32> %v6) 80 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v47, <16 x i32> undef) 81 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v48, i32 53019433) 82 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v49, i32 53019433) 83 %v52 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v51, <16 x i32> %v50) 84 %v53 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v52, <16 x i32> undef, i32 56) 85 %v54 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v35) 86 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32> %v53, <16 x i32> %v54) 87 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %v55, <16 x i32> %v8) 88 %v57 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 undef 89 store <16 x i32> %v56, <16 x i32>* %v57, align 64, !tbaa !0 90 %v58 = getelementptr <16 x i32>, <16 x i32>* %v2, i32 2 91 %v59 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 5 92 %v60 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> zeroinitializer, <16 x i32> %v38, i32 4) 93 %v61 = load <16 x i32>, <16 x i32>* %v40, align 64, !tbaa !0 94 %v62 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v60, <16 x i32> %v61) 95 %v63 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v62, <16 x i32> %v41, i32 4) 96 %v64 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v62, <16 x i32> %v41, i32 8) 97 %v65 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v62, <16 x i32> %v41, i32 12) 98 %v66 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v41, <16 x i32> %v63) 99 %v67 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v66, <16 x i32> %v64) 100 %v68 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v67, <16 x i32> %v65) 101 %v69 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v61, <16 x i32> %v39, i32 16) 102 %v70 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 1 103 %v71 = load <16 x i32>, <16 x i32>* %v70, align 64, !tbaa !0 104 %v72 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v68, <16 x i32> %v71) 105 %v73 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v68, <16 x i32> %v69) 106 %v74 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v72, i32 53019433) 107 %v75 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v73, i32 53019433) 108 %v76 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v75, <16 x i32> %v74) 109 store <16 x i32> %v76, <16 x i32>* %v58, align 64, !tbaa !0 110 %v77 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 7 111 %v78 = load <16 x i32>, <16 x i32>* %v77, align 64, !tbaa !0 112 %v79 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> undef, <16 x i32> undef) 113 %v80 = getelementptr <16 x i32>, <16 x i32>* %v2, i32 4 114 %v81 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 9 115 %v82 = load <16 x i32>, <16 x i32>* %v81, align 64, !tbaa !0 116 %v83 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v82, <16 x i32> %v78, i32 4) 117 %v84 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 10 118 %v85 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v83, <16 x i32> undef) 119 %v86 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v85, <16 x i32> %v79, i32 4) 120 %v87 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v85, <16 x i32> %v79, i32 8) 121 %v88 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v85, <16 x i32> %v79, i32 12) 122 %v89 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v79, <16 x i32> %v86) 123 %v90 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v89, <16 x i32> %v87) 124 %v91 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v90, <16 x i32> %v88) 125 %v92 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> undef, i32 16) 126 %v93 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v91, <16 x i32> zeroinitializer) 127 %v94 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v91, <16 x i32> %v92) 128 %v95 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v93, i32 53019433) 129 %v96 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v94, i32 53019433) 130 %v97 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> undef, <16 x i32> undef) 131 %v98 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v96, <16 x i32> %v95) 132 store <16 x i32> %v98, <16 x i32>* %v80, align 64, !tbaa !0 133 %v99 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 11 134 %v100 = load <16 x i32>, <16 x i32>* %v99, align 64, !tbaa !0 135 %v101 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v100, <16 x i32> %v82, i32 4) 136 %v102 = load <16 x i32>, <16 x i32>* %v84, align 64, !tbaa !0 137 %v103 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v101, <16 x i32> %v102) 138 %v104 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v103, <16 x i32> %v85, i32 4) 139 %v105 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v103, <16 x i32> %v85, i32 8) 140 %v106 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v85, <16 x i32> %v104) 141 %v107 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v106, <16 x i32> %v105) 142 %v108 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v107, <16 x i32> undef) 143 %v109 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v102, <16 x i32> undef, i32 16) 144 %v110 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v108, <16 x i32> %v78) 145 %v111 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v108, <16 x i32> %v109) 146 %v112 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v110, i32 53019433) 147 %v113 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %v7, <16 x i32> %v111, i32 53019433) 148 %v114 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v113, <16 x i32> %v112) 149 %v115 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v114, <16 x i32> undef, i32 56) 150 %v116 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v97) 151 %v117 = tail call <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32> %v115, <16 x i32> %v116) 152 %v118 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %v117, <16 x i32> %v8) 153 %v119 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 undef 154 store <16 x i32> %v118, <16 x i32>* %v119, align 64, !tbaa !0 155 %v120 = getelementptr <16 x i32>, <16 x i32>* %v2, i32 6 156 %v121 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> undef, <16 x i32> undef) 157 store <16 x i32> %v121, <16 x i32>* %v120, align 64, !tbaa !0 158 unreachable 159 160 b3: ; preds = %b1 161 unreachable 162 163 b4: ; preds = %b0 164 ret void 165 } 166 167 ; Function Attrs: nounwind readnone 168 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #0 169 170 ; Function Attrs: nounwind readnone 171 declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #0 172 173 ; Function Attrs: nounwind readnone 174 declare <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32>, <16 x i32>, i32) #0 175 176 ; Function Attrs: nounwind readnone 177 declare <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32>, <16 x i32>) #0 178 179 ; Function Attrs: nounwind readnone 180 declare <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32>, <16 x i32>) #0 181 182 ; Function Attrs: nounwind readnone 183 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0 184 185 attributes #0 = { nounwind readnone } 186 attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 187 188 !0 = !{!1, !1, i64 0} 189 !1 = !{!"omnipotent char", !2, i64 0} 190 !2 = !{!"Simple C/C++ TBAA"} 191
