1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2 3 ; Generate REG_SEQUENCE instead of combine 4 ; CHECK-NOT: combine(#0 5 6 ; Function Attrs: nounwind 7 define void @f0(i16* nocapture readonly %a0, i16* nocapture readonly %a1, i16* nocapture %a2, i16* nocapture readonly %a3, i32 %a4) #0 { 8 b0: 9 %v0 = lshr i32 %a4, 1 10 %v1 = icmp eq i32 %v0, 0 11 br i1 %v1, label %b3, label %b1 12 13 b1: ; preds = %b0 14 %v2 = bitcast i16* %a2 to i64* 15 %v3 = bitcast i16* %a1 to i64* 16 %v4 = bitcast i16* %a0 to i64* 17 br label %b2 18 19 b2: ; preds = %b2, %b1 20 %v5 = phi i32 [ 0, %b1 ], [ %v71, %b2 ] 21 %v6 = phi i64* [ %v4, %b1 ], [ %v9, %b2 ] 22 %v7 = phi i64* [ %v3, %b1 ], [ %v11, %b2 ] 23 %v8 = phi i64* [ %v2, %b1 ], [ %v70, %b2 ] 24 %v9 = getelementptr inbounds i64, i64* %v6, i32 1 25 %v10 = load i64, i64* %v6, align 8, !tbaa !0 26 %v11 = getelementptr inbounds i64, i64* %v7, i32 1 27 %v12 = load i64, i64* %v7, align 8, !tbaa !0 28 %v13 = trunc i64 %v10 to i32 29 %v14 = lshr i64 %v10, 32 30 %v15 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v13) 31 %v16 = trunc i64 %v12 to i32 32 %v17 = lshr i64 %v12, 32 33 %v18 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v16) 34 %v19 = trunc i64 %v15 to i32 35 %v20 = lshr i64 %v15, 32 36 %v21 = getelementptr inbounds i16, i16* %a3, i32 %v19 37 %v22 = load i16, i16* %v21, align 2, !tbaa !3 38 %v23 = trunc i64 %v20 to i32 39 %v24 = getelementptr inbounds i16, i16* %a3, i32 %v23 40 %v25 = load i16, i16* %v24, align 2, !tbaa !3 41 %v26 = trunc i64 %v18 to i32 42 %v27 = lshr i64 %v18, 32 43 %v28 = getelementptr inbounds i16, i16* %a3, i32 %v26 44 %v29 = load i16, i16* %v28, align 2, !tbaa !3 45 %v30 = trunc i64 %v27 to i32 46 %v31 = getelementptr inbounds i16, i16* %a3, i32 %v30 47 %v32 = load i16, i16* %v31, align 2, !tbaa !3 48 %v33 = zext i16 %v32 to i64 49 %v34 = shl nuw nsw i64 %v33, 32 50 %v35 = zext i16 %v29 to i64 51 %v36 = or i64 %v35, %v34 52 %v37 = zext i16 %v25 to i64 53 %v38 = shl nuw nsw i64 %v37, 32 54 %v39 = zext i16 %v22 to i64 55 %v40 = or i64 %v39, %v38 56 %v41 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v36, i64 %v40) 57 %v42 = getelementptr inbounds i64, i64* %v8, i32 1 58 store i64 %v41, i64* %v8, align 8, !tbaa !0 59 %v43 = trunc i64 %v14 to i32 60 %v44 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v43) 61 %v45 = trunc i64 %v17 to i32 62 %v46 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v45) 63 %v47 = trunc i64 %v44 to i32 64 %v48 = lshr i64 %v44, 32 65 %v49 = getelementptr inbounds i16, i16* %a3, i32 %v47 66 %v50 = load i16, i16* %v49, align 2, !tbaa !3 67 %v51 = trunc i64 %v48 to i32 68 %v52 = getelementptr inbounds i16, i16* %a3, i32 %v51 69 %v53 = load i16, i16* %v52, align 2, !tbaa !3 70 %v54 = trunc i64 %v46 to i32 71 %v55 = lshr i64 %v46, 32 72 %v56 = getelementptr inbounds i16, i16* %a3, i32 %v54 73 %v57 = load i16, i16* %v56, align 2, !tbaa !3 74 %v58 = trunc i64 %v55 to i32 75 %v59 = getelementptr inbounds i16, i16* %a3, i32 %v58 76 %v60 = load i16, i16* %v59, align 2, !tbaa !3 77 %v61 = zext i16 %v60 to i64 78 %v62 = shl nuw nsw i64 %v61, 32 79 %v63 = zext i16 %v57 to i64 80 %v64 = or i64 %v63, %v62 81 %v65 = zext i16 %v53 to i64 82 %v66 = shl nuw nsw i64 %v65, 32 83 %v67 = zext i16 %v50 to i64 84 %v68 = or i64 %v67, %v66 85 %v69 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v64, i64 %v68) 86 %v70 = getelementptr inbounds i64, i64* %v8, i32 2 87 store i64 %v69, i64* %v42, align 8, !tbaa !0 88 %v71 = add nsw i32 %v5, 1 89 %v72 = icmp ult i32 %v71, %v0 90 br i1 %v72, label %b2, label %b3 91 92 b3: ; preds = %b2, %b0 93 ret void 94 } 95 96 ; Function Attrs: nounwind readnone 97 declare i64 @llvm.hexagon.S2.vzxthw(i32) #1 98 99 ; Function Attrs: nounwind readnone 100 declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64) #1 101 102 attributes #0 = { nounwind "target-cpu"="hexagonv60" } 103 attributes #1 = { nounwind readnone } 104 105 !0 = !{!1, !1, i64 0} 106 !1 = !{!"omnipotent char", !2, i64 0} 107 !2 = !{!"Simple C/C++ TBAA"} 108 !3 = !{!4, !4, i64 0} 109 !4 = !{!"short", !1, i64 0} 110
