1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; Check for a sane output. This testcase used to cause a crash. 4 ; CHECK: vlut16 5 6 target triple = "hexagon-unknown--elf" 7 8 declare void @halide_malloc() local_unnamed_addr #0 9 10 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1 11 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 12 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1 13 declare <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32>, <32 x i32>) #1 14 declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1 15 declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) #1 16 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1 17 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1 18 19 define hidden void @fred(<32 x i32>* %a0, i32 %a1) #0 { 20 b0: 21 %v1 = ashr i32 %a1, 7 22 %v2 = shl nsw i32 %v1, 7 23 switch i32 undef, label %b7 [ 24 i32 1, label %b3 25 i32 2, label %b5 26 i32 3, label %b6 27 ] 28 29 b3: ; preds = %b0 30 unreachable 31 32 b4: ; preds = %b7 33 switch i32 undef, label %b9 [ 34 i32 1, label %b8 35 i32 2, label %b10 36 i32 3, label %b11 37 ] 38 39 b5: ; preds = %b0 40 unreachable 41 42 b6: ; preds = %b0 43 unreachable 44 45 b7: ; preds = %b0 46 br label %b4 47 48 b8: ; preds = %b4 49 br label %b12 50 51 b9: ; preds = %b4 52 br label %b12 53 54 b10: ; preds = %b4 55 br label %b12 56 57 b11: ; preds = %b4 58 br label %b12 59 60 b12: ; preds = %b11, %b10, %b9, %b8 61 br label %b13 62 63 b13: ; preds = %b14, %b12 64 br label %b14 65 66 b14: ; preds = %b13 67 br i1 undef, label %b15, label %b13 68 69 b15: ; preds = %b14 70 br label %b16 71 72 b16: ; preds = %b15 73 br i1 undef, label %b17, label %b18 74 75 b17: ; preds = %b16 76 unreachable 77 78 b18: ; preds = %b16 79 tail call void @halide_malloc() 80 br label %b19 81 82 b19: ; preds = %b18 83 %v21 = icmp sgt i32 %a1, 0 84 br i1 %v21, label %b20, label %b21 85 86 b20: ; preds = %b19 87 br label %b32 88 89 b21: ; preds = %b38, %b19 90 %v22 = zext i32 %v2 to i64 91 %v23 = lshr i64 %v22, 31 92 %v24 = shl nuw nsw i64 %v23, 1 93 %v25 = or i64 %v24, 0 94 %v26 = icmp ult i64 %v23, 2147483648 95 %v27 = mul nuw nsw i64 %v25, 3 96 %v28 = add nuw nsw i64 %v27, 0 97 %v29 = and i64 %v28, 133143986176 98 %v30 = icmp eq i64 %v29, 0 99 %v31 = and i1 %v26, %v30 100 br label %b39 101 102 b32: ; preds = %b20 103 %v33 = zext i32 %v2 to i64 104 %v34 = mul nuw nsw i64 %v33, 12 105 %v35 = icmp ult i64 %v34, 2147483648 106 %v36 = and i1 %v35, undef 107 br i1 %v36, label %b38, label %b37 108 109 b37: ; preds = %b32 110 ret void 111 112 b38: ; preds = %b32 113 tail call void @halide_malloc() 114 br label %b21 115 116 b39: ; preds = %b42, %b21 117 br label %b40 118 119 b40: ; preds = %b39 120 br i1 %v31, label %b42, label %b41 121 122 b41: ; preds = %b40 123 unreachable 124 125 b42: ; preds = %b40 126 %v43 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32> undef, <32 x i32> undef, i32 0) 127 %v44 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v43, <32 x i32> undef, <32 x i32> undef, i32 1) 128 %v45 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v44, <32 x i32> undef, <32 x i32> undef, i32 2) 129 %v46 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v45, <32 x i32> undef, <32 x i32> undef, i32 3) 130 %v47 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v46, <32 x i32> undef, <32 x i32> undef, i32 4) 131 %v48 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v47, <32 x i32> undef, <32 x i32> undef, i32 5) 132 %v49 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v48) 133 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32> undef, <32 x i32> %v49) #2 134 %v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2 135 %v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2 136 %v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2 137 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2 138 store <32 x i32> %v54, <32 x i32>* %a0, align 128 139 br label %b39 140 } 141 142 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } 143 attributes #1 = { nounwind readnone } 144 attributes #2 = { nounwind } 145
