1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 4 ; Test that register scvenging does not assert because of wrong 5 ; bits being set for Kill and Def bit vectors in replaceSuperBySubRegs 6 7 %s.0 = type { i32, i32*, [0 x i32], [0 x i32], [1 x i32] } 8 %s.1 = type { %s.2, %s.4, %s.5 } 9 %s.2 = type { %s.3 } 10 %s.3 = type { i32 } 11 %s.4 = type { i32 } 12 %s.5 = type { [0 x i32], [0 x i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*] } 13 14 @g0 = common global i32 0, align 4 15 @g1 = common global %s.0 zeroinitializer, align 4 16 @g2 = common global i32 0, align 4 17 @g3 = common global i32 0, align 4 18 @g4 = common global i32* null, align 4 19 @g5 = common global i32 0, align 4 20 @g6 = common global i32 0, align 4 21 22 ; Function Attrs: nounwind 23 define i32 @f0(%s.1* nocapture readonly %a0) #0 { 24 b0: 25 %v0 = alloca [0 x i32], align 4 26 %v1 = load i32, i32* @g0, align 4, !tbaa !0 27 %v2 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 0, i32 0, i32 0 28 %v3 = load i32, i32* %v2, align 4, !tbaa !0 29 %v4 = load i32*, i32** getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 1), align 4, !tbaa !4 30 %v5 = load i32, i32* @g2, align 4, !tbaa !0 31 %v6 = sub i32 0, %v5 32 %v7 = getelementptr inbounds i32, i32* %v4, i32 %v6 33 %v8 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 1, i32 0 34 %v9 = load i32, i32* %v8, align 4, !tbaa !0 35 switch i32 %v9, label %b17 [ 36 i32 0, label %b1 37 i32 1, label %b2 38 ] 39 40 b1: ; preds = %b0 41 store i32 0, i32* @g3, align 4, !tbaa !0 42 br label %b2 43 44 b2: ; preds = %b1, %b0 45 %v10 = icmp eq i32 %v1, 0 46 %v11 = icmp sgt i32 %v3, 0 47 %v12 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 0 48 %v13 = sdiv i32 %v3, 2 49 %v14 = add i32 %v13, -1 50 %v15 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 1 51 %v16 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 2 52 %v17 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 2, i32 1, i32 %v1 53 %v18 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 2, i32 1, i32 0 54 %v19 = sub i32 1, %v5 55 %v20 = getelementptr inbounds i32, i32* %v4, i32 %v19 56 %v21 = sdiv i32 %v3, 4 57 %v22 = icmp slt i32 %v3, -3 58 %v23 = add i32 %v3, -1 59 %v24 = lshr i32 %v23, 2 60 %v25 = mul i32 %v24, 4 61 %v26 = add i32 %v25, 4 62 %v27 = add i32 %v13, -2 63 %v28 = icmp slt i32 %v26, 0 64 %v29 = add i32 %v21, 1 65 %v30 = select i1 %v22, i32 1, i32 %v29 66 br label %b4 67 68 b3: ; preds = %b16 69 store i32 %v30, i32* @g3, align 4, !tbaa !0 70 br label %b4 71 72 b4: ; preds = %b13, %b3, %b2 73 %v31 = phi i32 [ undef, %b2 ], [ %v87, %b3 ], [ %v87, %b13 ] 74 %v32 = phi i32 [ undef, %b2 ], [ %v86, %b3 ], [ %v86, %b13 ] 75 %v33 = phi i32 [ undef, %b2 ], [ %v35, %b3 ], [ %v35, %b13 ] 76 %v34 = phi i32 [ undef, %b2 ], [ %v89, %b3 ], [ %v89, %b13 ] 77 %v35 = phi i32 [ undef, %b2 ], [ %v94, %b3 ], [ %v65, %b13 ] 78 br i1 %v10, label %b6, label %b5 79 80 b5: ; preds = %b5, %b4 81 br label %b5 82 83 b6: ; preds = %b4 84 br i1 %v11, label %b8, label %b7 85 86 b7: ; preds = %b6 87 store i32 0, i32* @g3, align 4, !tbaa !0 88 br label %b11 89 90 b8: ; preds = %b6 91 store i32 %v26, i32* @g3, align 4, !tbaa !0 92 br i1 %v28, label %b9, label %b11 93 94 b9: ; preds = %b8 95 %v36 = load i32*, i32** @g4, align 4, !tbaa !7 96 br label %b10 97 98 b10: ; preds = %b10, %b9 99 %v37 = phi i32 [ %v26, %b9 ], [ %v45, %b10 ] 100 %v38 = phi i32 [ %v34, %b9 ], [ %v44, %b10 ] 101 %v39 = add nsw i32 %v37, %v33 102 %v40 = shl i32 %v39, 1 103 %v41 = getelementptr inbounds i32, i32* %v36, i32 %v40 104 %v42 = load i32, i32* %v41, align 4, !tbaa !0 105 %v43 = icmp slt i32 %v42, %v31 106 %v44 = select i1 %v43, i32 0, i32 %v38 107 %v45 = add nsw i32 %v37, 1 108 store i32 %v45, i32* @g3, align 4, !tbaa !0 109 %v46 = icmp slt i32 %v45, 0 110 br i1 %v46, label %b10, label %b11 111 112 b11: ; preds = %b10, %b8, %b7 113 %v47 = phi i32 [ %v26, %b8 ], [ 0, %b7 ], [ 0, %b10 ] 114 %v48 = phi i32 [ %v34, %b8 ], [ %v34, %b7 ], [ %v44, %b10 ] 115 %v49 = load i32, i32* @g5, align 4, !tbaa !0 116 %v50 = icmp slt i32 %v13, %v49 117 %v51 = icmp slt i32 %v47, %v14 118 %v52 = and i1 %v50, %v51 119 br i1 %v52, label %b12, label %b13 120 121 b12: ; preds = %b11 122 %v53 = sub i32 %v27, %v47 123 %v54 = lshr i32 %v53, 1 124 %v55 = mul i32 %v54, 2 125 %v56 = add i32 %v47, 2 126 %v57 = add i32 %v56, %v55 127 store i32 %v57, i32* @g3, align 4, !tbaa !0 128 br label %b13 129 130 b13: ; preds = %b12, %b11 131 %v58 = shl i32 %v35, 2 132 %v59 = load i32*, i32** @g4, align 4, !tbaa !7 133 %v60 = getelementptr inbounds i32, i32* %v59, i32 %v58 134 %v61 = load i32, i32* %v60, align 4, !tbaa !0 135 %v62 = load i32, i32* %v7, align 4, !tbaa !0 136 %v63 = add nsw i32 %v62, %v61 137 %v64 = add nsw i32 %v63, %v32 138 store i32 %v64, i32* %v15, align 4, !tbaa !0 139 %v65 = add i32 %v35, -1 140 %v66 = getelementptr inbounds i32, i32* %v59, i32 %v65 141 %v67 = load i32, i32* %v66, align 4, !tbaa !0 142 %v68 = sub i32 %v49, %v5 143 %v69 = getelementptr inbounds i32, i32* %v4, i32 %v68 144 %v70 = load i32, i32* %v69, align 4, !tbaa !0 145 %v71 = add nsw i32 %v70, %v67 146 %v72 = load i32, i32* %v16, align 4, !tbaa !0 147 %v73 = add nsw i32 %v71, %v72 148 store i32 %v73, i32* %v16, align 4, !tbaa !0 149 %v74 = load i32, i32* @g6, align 4, !tbaa !0 150 %v75 = load i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*, i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)** %v17, align 4, !tbaa !7 151 %v76 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), align 4, !tbaa !0 152 %v77 = call i32 %v75(i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), i32* null, i32* null, i32* null, i32* null, i32 %v76, i32* null) #0 153 %v78 = load i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*, i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)** %v18, align 4, !tbaa !7 154 %v79 = inttoptr i32 %v74 to i32* 155 %v80 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), align 4, !tbaa !0 156 %v81 = call i32 %v78(i32* getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 4, i32 0), i32* null, i32* null, i32* null, i32* %v79, i32 %v80, i32* %v12) #0 157 %v82 = load i32*, i32** @g4, align 4, !tbaa !7 158 %v83 = getelementptr inbounds i32, i32* %v82, i32 %v58 159 %v84 = load i32, i32* %v83, align 4, !tbaa !0 160 %v85 = load i32, i32* %v20, align 4, !tbaa !0 161 %v86 = add nsw i32 %v85, %v84 162 store i32 %v86, i32* %v15, align 4, !tbaa !0 163 %v87 = load i32, i32* %v12, align 4, !tbaa !0 164 %v88 = icmp eq i32 %v87, 0 165 %v89 = select i1 %v88, i32 %v48, i32 1 166 store i32 %v89, i32* @g5, align 4, !tbaa !0 167 store i32 0, i32* @g3, align 4, !tbaa !0 168 br i1 %v22, label %b4, label %b14 169 170 b14: ; preds = %b16, %b13 171 %v90 = phi i32 [ %v95, %b16 ], [ 0, %b13 ] 172 %v91 = phi i32 [ %v94, %b16 ], [ %v65, %b13 ] 173 br i1 %v88, label %b16, label %b15 174 175 b15: ; preds = %b14 176 %v92 = mul i32 %v90, -4 177 %v93 = add nsw i32 %v92, 1 178 br label %b16 179 180 b16: ; preds = %b15, %b14 181 %v94 = phi i32 [ %v93, %b15 ], [ %v91, %b14 ] 182 %v95 = add nsw i32 %v90, 1 183 %v96 = icmp slt i32 %v90, %v21 184 br i1 %v96, label %b14, label %b3 185 186 b17: ; preds = %b0 187 ret i32 undef 188 } 189 190 attributes #0 = { nounwind } 191 192 !0 = !{!1, !1, i64 0} 193 !1 = !{!"int", !2, i64 0} 194 !2 = !{!"omnipotent char", !3, i64 0} 195 !3 = !{!"Simple C/C++ TBAA"} 196 !4 = !{!5, !6, i64 4} 197 !5 = !{!"", !1, i64 0, !6, i64 4, !2, i64 8, !2, i64 8, !2, i64 8} 198 !6 = !{!"any pointer", !2, i64 0} 199 !7 = !{!6, !6, i64 0} 200
