1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 4 ; Test that the splitVecPredRegs pass in the Hexagon Peephole pass does not 5 ; move a vector predicate definition illegally, which ends up causing an assert 6 ; later. The assert occurs because there is a use of a register that does not 7 ; have a correct definition. 8 9 define void @f0() local_unnamed_addr #0 { 10 b0: 11 br label %b1 12 13 b1: ; preds = %b0 14 br i1 undef, label %b2, label %b3 15 16 b2: ; preds = %b1 17 unreachable 18 19 b3: ; preds = %b1 20 br label %b4 21 22 b4: ; preds = %b3 23 br label %b5 24 25 b5: ; preds = %b4 26 br i1 undef, label %b13, label %b6 27 28 b6: ; preds = %b5 29 br label %b7 30 31 b7: ; preds = %b6 32 br label %b8 33 34 b8: ; preds = %b7 35 %v0 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> undef, i32 -1) 36 br i1 undef, label %b9, label %b11 37 38 b9: ; preds = %b8 39 br label %b12 40 41 b10: ; preds = %b12 42 br label %b11 43 44 b11: ; preds = %b10, %b8 45 %v1 = phi <512 x i1> [ %v0, %b8 ], [ undef, %b10 ] 46 %v2 = tail call <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1> %v1, <512 x i1> undef) 47 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vaddbq(<512 x i1> %v2, <16 x i32> undef, <16 x i32> undef) 48 %v4 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> %v3, i32 undef) 49 %v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> undef, i32 undef) 50 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v5, <16 x i32> undef) 51 %v7 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %v6, <16 x i32> undef) 52 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32> %v7, <16 x i32> undef) 53 %v9 = tail call <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32> undef, <16 x i32> %v8) 54 %v10 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v9) 55 %v11 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %v10, <16 x i32> undef) 56 %v12 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v11, i32 -1) 57 %v13 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1> %v12, i32 undef) 58 tail call void @llvm.hexagon.V6.vmaskedstoreq(<512 x i1> undef, i8* undef, <16 x i32> %v13) 59 unreachable 60 61 b12: ; preds = %b12, %b9 62 %v14 = phi i32 [ %v15, %b12 ], [ 0, %b9 ] 63 %v15 = add nuw nsw i32 %v14, 1 64 %v16 = icmp slt i32 %v15, undef 65 br i1 %v16, label %b12, label %b10 66 67 b13: ; preds = %b5 68 ret void 69 } 70 71 ; Function Attrs: nounwind readnone 72 declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 73 74 ; Function Attrs: nounwind readnone 75 declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1 76 77 ; Function Attrs: nounwind readnone 78 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 79 80 ; Function Attrs: nounwind readnone 81 declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 82 83 ; Function Attrs: argmemonly nounwind 84 declare void @llvm.hexagon.V6.vmaskedstoreq(<512 x i1>, i8*, <16 x i32>) #2 85 86 ; Function Attrs: nounwind readnone 87 declare <16 x i32> @llvm.hexagon.V6.vaddbq(<512 x i1>, <16 x i32>, <16 x i32>) #1 88 89 ; Function Attrs: nounwind readnone 90 declare <16 x i32> @llvm.hexagon.V6.vor(<16 x i32>, <16 x i32>) #1 91 92 ; Function Attrs: nounwind readnone 93 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 94 95 ; Function Attrs: nounwind readnone 96 declare <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32>, <16 x i32>) #1 97 98 ; Function Attrs: nounwind readnone 99 declare <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32>, <16 x i32>) #1 100 101 ; Function Attrs: nounwind readnone 102 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 103 104 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 105 attributes #1 = { nounwind readnone } 106 attributes #2 = { argmemonly nounwind } 107
