1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; Check if S4_subi_asl_ri is being generated correctly. 4 5 ; CHECK-LABEL: yes_sub_asl 6 ; CHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1)) 7 8 ; CHECK-LABEL: no_sub_asl 9 ; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1) 10 ; CHECK: r{{[0-9]+}} = sub([[REG2]],r{{[0-9]+}}) 11 12 %struct.rtx_def = type { i16, i8 } 13 14 @this_insn_number = external global i32, align 4 15 16 ; Function Attrs: nounwind 17 define void @yes_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 { 18 entry: 19 %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0 20 %0 = load i16, i16* %code, align 4 21 switch i16 %0, label %return [ 22 i16 2, label %if.end 23 i16 5, label %if.end 24 ] 25 26 if.end: 27 %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0 28 %1 = load i16, i16* %code6, align 4 29 %cmp8 = icmp eq i16 %1, 56 30 %conv9 = zext i1 %cmp8 to i32 31 %2 = load i32, i32* @this_insn_number, align 4 32 %3 = mul i32 %2, -2 33 %sub = add nsw i32 %conv9, %3 34 tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2 35 br label %return 36 37 return: 38 ret void 39 } 40 41 declare void @reg_is_born(%struct.rtx_def*, i32) #1 42 43 ; Function Attrs: nounwind 44 define void @no_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 { 45 entry: 46 %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0 47 %0 = load i16, i16* %code, align 4 48 switch i16 %0, label %return [ 49 i16 2, label %if.end 50 i16 5, label %if.end 51 ] 52 53 if.end: 54 %1 = load i32, i32* @this_insn_number, align 4 55 %mul = mul nsw i32 %1, 2 56 %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0 57 %2 = load i16, i16* %code6, align 4 58 %cmp8 = icmp eq i16 %2, 56 59 %conv9 = zext i1 %cmp8 to i32 60 %sub = sub nsw i32 %mul, %conv9 61 tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2 62 br label %return 63 64 return: 65 ret void 66 } 67 68 attributes #0 = { nounwind "target-cpu"="hexagonv5" } 69 attributes #1 = { "target-cpu"="hexagonv5" } 70 attributes #2 = { nounwind } 71
