1 ; RUN: llc -march=hexagon -rdf-opt=0 -disable-hexagon-misched < %s | FileCheck %s 2 3 ; Test that we generate the correct code when a loop carried value 4 ; is scheduled one stage earlier than it's use. The code in 5 ; isLoopCarried was returning false in this case, and the generated 6 ; code was missing an copy. 7 8 ; CHECK: loop0(.LBB0_[[LOOP:.]], 9 ; CHECK: .LBB0_[[LOOP]]: 10 ; CHECK: += mpy([[REG0:(r[0-9]+)]],r{{[0-9]+}}) 11 ; CHECK: [[REG0]] = r{{[0-9]+}} 12 ; CHECK-NOT: [[REG0]] = memw 13 ; CHECK: endloop0 14 15 @g0 = external global [256 x i32], align 8 16 17 define void @f0() #0 { 18 b0: 19 br label %b1 20 21 b1: ; preds = %b1, %b0 22 br i1 undef, label %b2, label %b1 23 24 b2: ; preds = %b1 25 br label %b3 26 27 b3: ; preds = %b3, %b2 28 %v0 = phi i32* [ getelementptr inbounds ([256 x i32], [256 x i32]* @g0, i32 0, i32 0), %b2 ], [ %v1, %b3 ] 29 %v1 = getelementptr i32, i32* %v0, i32 6 30 br i1 undef, label %b4, label %b3 31 32 b4: ; preds = %b3 33 br i1 undef, label %b6, label %b5 34 35 b5: ; preds = %b5, %b4 36 %v2 = phi i64 [ %v19, %b5 ], [ undef, %b4 ] 37 %v3 = phi i32* [ %v8, %b5 ], [ %v1, %b4 ] 38 %v4 = phi i32 [ %v9, %b5 ], [ undef, %b4 ] 39 %v5 = phi i32 [ %v11, %b5 ], [ undef, %b4 ] 40 %v6 = phi i32 [ %v5, %b5 ], [ undef, %b4 ] 41 %v7 = phi i32 [ %v10, %b5 ], [ 0, %b4 ] 42 %v8 = getelementptr i32, i32* %v3, i32 1 43 %v9 = add nsw i32 %v4, 1 44 %v10 = load i32, i32* %v8, align 4 45 %v11 = load i32, i32* null, align 4 46 %v12 = sext i32 %v6 to i64 47 %v13 = sext i32 %v10 to i64 48 %v14 = sext i32 %v7 to i64 49 %v15 = mul nsw i64 %v14, %v12 50 %v16 = add i64 %v12, %v2 51 %v17 = add i64 %v16, %v13 52 %v18 = add i64 %v17, 0 53 %v19 = add i64 %v18, %v15 54 %v20 = icmp eq i32 %v9, 128 55 br i1 %v20, label %b6, label %b5 56 57 b6: ; preds = %b5, %b4 58 %v21 = phi i64 [ undef, %b4 ], [ %v19, %b5 ] 59 unreachable 60 } 61 62 attributes #0 = { nounwind "target-cpu"="hexagonv62" } 63
