1 ; RUN: llc -march=hexagon -O3 < %s 2 ; REQUIRES: asserts 3 4 ; Don't change the dependences if it's going to cause a cycle. 5 6 ; Function Attrs: nounwind 7 define void @f0(i8* nocapture %a0, i32 %a1) #0 { 8 b0: 9 br i1 undef, label %b1, label %b2 10 11 b1: ; preds = %b1, %b0 12 %v0 = phi i8* [ undef, %b1 ], [ undef, %b0 ] 13 %v1 = phi i32 [ %v20, %b1 ], [ 1, %b0 ] 14 %v2 = phi i8* [ %v6, %b1 ], [ %a0, %b0 ] 15 %v3 = load i8, i8* %v2, align 1 16 %v4 = zext i8 %v3 to i32 17 %v5 = mul nsw i32 %v4, 3 18 %v6 = getelementptr inbounds i8, i8* %v2, i32 1 19 %v7 = load i8, i8* %v6, align 1 20 %v8 = zext i8 %v7 to i32 21 %v9 = add i32 %v8, 2 22 %v10 = add i32 %v9, %v5 23 %v11 = lshr i32 %v10, 2 24 %v12 = trunc i32 %v11 to i8 25 %v13 = getelementptr inbounds i8, i8* undef, i32 2 26 store i8 %v12, i8* %v0, align 1 27 %v14 = load i8, i8* %v2, align 1 28 %v15 = zext i8 %v14 to i32 29 %v16 = add i32 %v15, 2 30 %v17 = add i32 %v16, 0 31 %v18 = lshr i32 %v17, 2 32 %v19 = trunc i32 %v18 to i8 33 store i8 %v19, i8* %v13, align 1 34 %v20 = add i32 %v1, 1 35 %v21 = icmp eq i32 %v20, %a1 36 br i1 %v21, label %b2, label %b1 37 38 b2: ; preds = %b1, %b0 39 ret void 40 } 41 42 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 43
