1 ; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner < %s 2 ; REQUIRES: asserts 3 4 ; Function Attrs: nounwind 5 define void @f0() #0 { 6 b0: 7 br i1 undef, label %b1, label %b2 8 9 b1: ; preds = %b0 10 unreachable 11 12 b2: ; preds = %b0 13 br i1 undef, label %b3, label %b4 14 15 b3: ; preds = %b2 16 unreachable 17 18 b4: ; preds = %b2 19 br i1 undef, label %b5, label %b6 20 21 b5: ; preds = %b4 22 unreachable 23 24 b6: ; preds = %b4 25 br label %b7 26 27 b7: ; preds = %b7, %b6 28 br i1 undef, label %b8, label %b7 29 30 b8: ; preds = %b7 31 br i1 undef, label %b15, label %b9 32 33 b9: ; preds = %b8 34 br label %b10 35 36 b10: ; preds = %b10, %b9 37 br i1 undef, label %b11, label %b10 38 39 b11: ; preds = %b10 40 br label %b12 41 42 b12: ; preds = %b12, %b11 43 br i1 undef, label %b13, label %b12 44 45 b13: ; preds = %b13, %b12 46 %v0 = phi i32 [ %v5, %b13 ], [ 0, %b12 ] 47 %v1 = getelementptr inbounds [11 x i32], [11 x i32]* undef, i32 0, i32 %v0 48 %v2 = load i32, i32* %v1, align 4 49 %v3 = add i32 %v2, 1 50 %v4 = lshr i32 %v3, 1 51 store i32 %v4, i32* %v1, align 4 52 store i32 0, i32* %v1, align 4 53 %v5 = add nsw i32 %v0, 1 54 %v6 = icmp eq i32 %v5, 11 55 br i1 %v6, label %b14, label %b13 56 57 b14: ; preds = %b13 58 br label %b15 59 60 b15: ; preds = %b14, %b8 61 ret void 62 } 63 64 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 65
