1 ; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=1 < %s | FileCheck %s 2 3 ; Test that we update the offset correctly for loads that are 4 ; moved past stores. In these cases, we change the dependences 5 ; to make it easier to move the instructions, and we have to update 6 ; the register/offsets correctly after the schedule is finalized. 7 8 @g0 = common global [400 x i32] zeroinitializer, align 8 9 @g1 = common global [400 x i32] zeroinitializer, align 8 10 11 ; Function Attrs: nounwind 12 define void @f0() #0 { 13 b0: 14 br label %b2 15 16 b1: ; preds = %b2 17 ret void 18 19 ; CHECK: loop0(.LBB0_[[LOOP:.]], 20 ; CHECK: .LBB0_[[LOOP]]: 21 ; CHECK: = memd([[REG1:(r[0-9]+)]]+#8) 22 ; CHECK: memd([[REG1]]++#8) = 23 ; CHECK: }{{[ \t]*}}:endloop 24 25 b2: ; preds = %b2, %b0 26 %v0 = phi i32* [ getelementptr inbounds ([400 x i32], [400 x i32]* @g0, i32 0, i32 0), %b0 ], [ %v11, %b2 ] 27 %v1 = phi i32* [ getelementptr inbounds ([400 x i32], [400 x i32]* @g1, i32 0, i32 0), %b0 ], [ %v12, %b2 ] 28 %v2 = phi i32 [ 0, %b0 ], [ %v9, %b2 ] 29 %v3 = bitcast i32* %v0 to <2 x i32>* 30 %v4 = load <2 x i32>, <2 x i32>* %v3, align 8 31 %v5 = mul <2 x i32> %v4, <i32 7, i32 7> 32 %v6 = bitcast i32* %v1 to <2 x i32>* 33 %v7 = load <2 x i32>, <2 x i32>* %v6, align 8 34 %v8 = add <2 x i32> %v7, %v5 35 store <2 x i32> %v8, <2 x i32>* %v6, align 8 36 %v9 = add nsw i32 %v2, 2 37 %v10 = icmp slt i32 %v2, 398 38 %v11 = getelementptr i32, i32* %v0, i32 2 39 %v12 = getelementptr i32, i32* %v1, i32 2 40 br i1 %v10, label %b2, label %b1 41 } 42 43 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 44
