Home | History | Annotate | Download | only in Hexagon
      1 ; XFAIL: *
      2 ; Needs some fixed in the pipeliner.
      3 ; RUN: llc -march=hexagon < %s | FileCheck %s
      4 
      5 ; CHECK: endloop0
      6 ; CHECK: vmem
      7 ; CHECK: vmem([[REG:r([0-9]+)]]+#1) =
      8 ; CHECK: vmem([[REG]]+#0) =
      9 
     10 define void @f0(i32 %a0) local_unnamed_addr #0 {
     11 b0:
     12   br label %b1
     13 
     14 b1:                                               ; preds = %b1, %b0
     15   %v0 = phi i32 [ %v33, %b1 ], [ %a0, %b0 ]
     16   %v1 = phi <16 x i32>* [ %v32, %b1 ], [ undef, %b0 ]
     17   %v2 = phi <16 x i32>* [ %v23, %b1 ], [ undef, %b0 ]
     18   %v3 = phi <16 x i32>* [ %v10, %b1 ], [ undef, %b0 ]
     19   %v4 = phi <16 x i32>* [ %v8, %b1 ], [ null, %b0 ]
     20   %v5 = phi <32 x i32> [ %v12, %b1 ], [ undef, %b0 ]
     21   %v6 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v5)
     22   %v7 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v6, <16 x i32> undef, i32 6)
     23   %v8 = getelementptr inbounds <16 x i32>, <16 x i32>* %v4, i32 1
     24   %v9 = load <16 x i32>, <16 x i32>* %v4, align 64
     25   %v10 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 1
     26   %v11 = load <16 x i32>, <16 x i32>* %v3, align 64
     27   %v12 = tail call <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32> %v11, <16 x i32> %v9)
     28   %v13 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v12)
     29   %v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v13, <16 x i32> undef)
     30   %v15 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v14, <16 x i32> undef, i32 4)
     31   %v16 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v14, <16 x i32> %v15)
     32   %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v14, <16 x i32> undef, i32 4)
     33   %v18 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v16, <16 x i32> undef, i32 2)
     34   %v19 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v17)
     35   %v20 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v18, <16 x i32> %v19)
     36   %v21 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
     37   %v22 = load <16 x i32>, <16 x i32>* %v2, align 64
     38   %v23 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 2
     39   %v24 = load <16 x i32>, <16 x i32>* %v21, align 64
     40   %v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v22, <16 x i32> %v7)
     41   %v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v24, <16 x i32> undef)
     42   %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v25, <16 x i32> %v20)
     43   %v28 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v26, <16 x i32> %v20)
     44   store <16 x i32> %v27, <16 x i32>* %v2, align 64
     45   store <16 x i32> %v28, <16 x i32>* %v21, align 64
     46   %v29 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %v27, i32 17760527)
     47   %v30 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %v28, i32 17760527)
     48   %v31 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v30, <16 x i32> %v29)
     49   %v32 = getelementptr inbounds <16 x i32>, <16 x i32>* %v1, i32 1
     50   store <16 x i32> %v31, <16 x i32>* %v1, align 64
     51   %v33 = add nsw i32 %v0, -64
     52   %v34 = icmp sgt i32 %v0, 192
     53   br i1 %v34, label %b1, label %b2
     54 
     55 b2:                                               ; preds = %b1
     56   unreachable
     57 }
     58 
     59 ; Function Attrs: nounwind readnone
     60 declare <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32>, <16 x i32>) #1
     61 
     62 ; Function Attrs: nounwind readnone
     63 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
     64 
     65 ; Function Attrs: nounwind readnone
     66 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
     67 
     68 ; Function Attrs: nounwind readnone
     69 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
     70 
     71 ; Function Attrs: nounwind readnone
     72 declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1
     73 
     74 ; Function Attrs: nounwind readnone
     75 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
     76 
     77 ; Function Attrs: nounwind readnone
     78 declare <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32>, i32) #1
     79 
     80 ; Function Attrs: nounwind readnone
     81 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
     82 
     83 attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
     84 attributes #1 = { nounwind readnone }
     85