1 ; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=3 < %s | FileCheck %s 2 3 %s.0 = type { i16, i8, i8, i16, i8, i8, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16, i8, i8, %s.1, [2 x [16 x %s.2]], i32 (i8*, i8*, i8*, i8*, i8*)*, %s.3*, %s.3*, [120 x i8], i8, i8, %s.4*, [2 x [120 x [8 x i8]]], [56 x i8], [2 x [121 x %s.5]], [2 x %s.5], %s.5*, %s.5*, i32, i32, i16, i8, i8, %s.7, %s.9, %s.11, %s.8*, %s.8* } 4 %s.1 = type { i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, [16 x i8], i8, [4 x i8], [32 x i16], [32 x i16], [2 x i8], [4 x i8], [2 x [4 x i8]], [2 x [4 x i8]], i32, i32, i16, i8 } 5 %s.2 = type { [2 x i16] } 6 %s.3 = type { i16*, i16*, i32, i32 } 7 %s.4 = type { i8*, i8*, i8*, i32, i32, i32, i32 } 8 %s.5 = type { %s.6, [2 x [4 x %s.2]], [2 x [2 x i8]], [2 x i8] } 9 %s.6 = type { i8, i8, i8, i8, i8, i8, i8, i8, i32 } 10 %s.7 = type { [12 x %s.8], [4 x %s.8], [2 x %s.8], [4 x %s.8], [6 x %s.8], [2 x [7 x %s.8]], [4 x %s.8], [3 x [4 x %s.8]], [3 x %s.8], [3 x %s.8] } 11 %s.8 = type { i8, i8 } 12 %s.9 = type { [371 x %s.8], [6 x %s.10] } 13 %s.10 = type { %s.8*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } 14 %s.11 = type { i32, i32, i8* } 15 16 ; Function Attrs: nounwind 17 define void @f0(%s.0* %a0) #0 { 18 b0: 19 %v0 = load i8, i8* undef, align 1, !tbaa !0 20 %v1 = icmp eq i8 %v0, 1 21 br i1 %v1, label %b1, label %b2 22 23 ; CHECK: loop0(.LBB0_[[LOOP:.]], 24 ; CHECK: .LBB0_[[LOOP]]: 25 ; CHECK: memh([[REG0:(r[0-9]+)]]+#0) = #0 26 ; CHECK: }{{[ \t]*}}:endloop0 27 28 b1: ; preds = %b1, %b0 29 %v2 = phi i16* [ %v17, %b1 ], [ undef, %b0 ] 30 %v3 = phi i32 [ %v18, %b1 ], [ 0, %b0 ] 31 %v4 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 25, i32 10, i32 %v3 32 %v5 = load i8, i8* %v4, align 1, !tbaa !0 33 %v6 = zext i8 %v5 to i16 34 %v7 = add nsw i32 %v3, 1 35 %v8 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 25, i32 10, i32 %v7 36 %v9 = load i8, i8* %v8, align 1, !tbaa !0 37 %v10 = or i16 0, %v6 38 %v11 = load i8, i8* undef, align 1, !tbaa !0 39 %v12 = zext i8 %v11 to i16 40 %v13 = shl nuw i16 %v12, 8 41 %v14 = or i16 %v10, %v13 42 %v15 = or i16 %v14, 0 43 %v16 = getelementptr inbounds i16, i16* %v2, i32 1 44 store i16* %v16, i16** null, align 4, !tbaa !3 45 store i16 %v15, i16* %v2, align 2, !tbaa !5 46 %v17 = getelementptr inbounds i16, i16* %v2, i32 2 47 store i16* %v17, i16** null, align 4, !tbaa !3 48 store i16 0, i16* %v16, align 2, !tbaa !5 49 %v18 = add nsw i32 %v3, 8 50 %v19 = icmp slt i32 %v18, undef 51 br i1 %v19, label %b1, label %b2 52 53 b2: ; preds = %b1, %b0 54 ret void 55 } 56 57 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 58 59 !0 = !{!1, !1, i64 0} 60 !1 = !{!"omnipotent char", !2} 61 !2 = !{!"Simple C/C++ TBAA"} 62 !3 = !{!4, !4, i64 0} 63 !4 = !{!"any pointer", !1} 64 !5 = !{!6, !6, i64 0} 65 !6 = !{!"short", !1} 66
