1 ; RUN: llc -march=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 > /dev/null | FileCheck %s 2 ; REQUIRES: asserts 3 4 ; Test that the phi in the first epilog block is getter the correct 5 ; value from the kernel block. In this bug, the phi was using the value 6 ; defined in the loop instead of the Phi valued defined in the kernel. 7 ; We need to use the kernel's phi value (if the Phi in the kernel is the 8 ; last definition). 9 10 ; CHECK: New block 11 ; CHECK: %[[REG:([0-9]+)]]:intregs = PHI %{{.*}}, %[[REG1:([0-9]+)]] 12 ; CHECK: %[[REG1]]:intregs = A2_addi 13 ; CHECK: epilog: 14 ; CHECK: %{{[0-9]+}}:intregs = PHI %{{.*}}, %[[REG]] 15 16 define void @f0(i32 %a0, i32 %a1) #0 { 17 b0: 18 %v0 = icmp sgt i32 %a0, 64 19 br i1 %v0, label %b1, label %b3 20 21 b1: ; preds = %b0 22 br label %b2 23 24 b2: ; preds = %b2, %b1 25 %v1 = phi i32 [ %a0, %b1 ], [ %v13, %b2 ] 26 %v2 = phi <16 x i32>* [ null, %b1 ], [ %v3, %b2 ] 27 %v3 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1 28 %v4 = load <16 x i32>, <16 x i32>* %v2, align 64 29 %v5 = load <16 x i32>, <16 x i32>* undef, align 64 30 %v6 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v5, <16 x i32> undef, i32 1) 31 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v6) 32 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v7, i32 undef) 33 %v9 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v8, <32 x i32> undef, i32 undef) 34 %v10 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v9, <16 x i32> zeroinitializer, i32 undef) 35 %v11 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v10) 36 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v11, i32 %a1) 37 store <16 x i32> %v12, <16 x i32>* null, align 64 38 %v13 = add nsw i32 %v1, -64 39 %v14 = icmp sgt i32 %v13, 64 40 br i1 %v14, label %b2, label %b3 41 42 b3: ; preds = %b2, %b0 43 ret void 44 } 45 46 ; Function Attrs: nounwind readnone 47 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0 48 49 ; Function Attrs: nounwind readnone 50 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0 51 52 ; Function Attrs: nounwind readnone 53 declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #0 54 55 ; Function Attrs: nounwind readnone 56 declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #0 57 58 ; Function Attrs: nounwind readnone 59 declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #0 60 61 ; Function Attrs: nounwind readnone 62 declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #0 63 64 ; Function Attrs: nounwind readnone 65 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0 66 67 attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 68
