1 ; RUN: llc -march=hexagon -enable-pipeliner < %s 2 ; REQUIRES: asserts 3 4 ; Test that the pipeliner doesn't ICE due to incorrect PHI 5 ; generation code that attemps to reuse an exsting PHI. 6 ; Similar to the other swp-epillog-reuse test, but from a 7 ; different test case. 8 9 ; Function Attrs: nounwind readnone 10 declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0 11 12 ; Function Attrs: nounwind 13 define void @f0() #1 { 14 b0: 15 br label %b1 16 17 b1: ; preds = %b1, %b0 18 br i1 undef, label %b2, label %b1 19 20 b2: ; preds = %b2, %b1 21 br i1 undef, label %b3, label %b2 22 23 b3: ; preds = %b3, %b2 24 %v0 = phi i16 [ %v10, %b3 ], [ undef, %b2 ] 25 %v1 = phi i16 [ %v0, %b3 ], [ undef, %b2 ] 26 %v2 = phi i32 [ %v26, %b3 ], [ undef, %b2 ] 27 %v3 = phi i32* [ undef, %b3 ], [ undef, %b2 ] 28 %v4 = phi i16* [ %v5, %b3 ], [ undef, %b2 ] 29 %v5 = getelementptr inbounds i16, i16* %v4, i32 1 30 %v6 = sext i16 %v1 to i32 31 %v7 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 0, i32 %v6, i32 undef) 32 %v8 = getelementptr inbounds i16, i16* %v4, i32 2 33 %v9 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v7, i32 undef, i32 undef) 34 %v10 = load i16, i16* %v8, align 2, !tbaa !0 35 %v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v9, i32 undef, i32 undef) 36 %v12 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v11, i32 undef) 37 %v13 = getelementptr [166 x i32], [166 x i32]* null, i32 0, i32 undef 38 %v14 = load i32, i32* %v13, align 4 39 %v15 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v14, i32 undef) 40 %v16 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v15, i32 15) 41 %v17 = call i32 @llvm.hexagon.A2.sat(i64 %v16) 42 %v18 = call i32 @llvm.hexagon.A2.subsat(i32 %v12, i32 %v17) 43 %v19 = getelementptr [166 x i32], [166 x i32]* null, i32 0, i32 undef 44 %v20 = load i32, i32* %v19, align 4 45 %v21 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v20, i32 0) 46 %v22 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v21, i32 15) 47 %v23 = call i32 @llvm.hexagon.A2.sat(i64 %v22) 48 %v24 = call i32 @llvm.hexagon.A2.subsat(i32 %v18, i32 %v23) 49 %v25 = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v24, i32 undef) 50 store i32 %v25, i32* %v3, align 4, !tbaa !4 51 %v26 = add i32 %v2, 1 52 %v27 = icmp eq i32 %v26, 164 53 br i1 %v27, label %b4, label %b3 54 55 b4: ; preds = %b3 56 call void @llvm.trap() 57 unreachable 58 } 59 60 ; Function Attrs: nounwind readnone 61 declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #0 62 63 ; Function Attrs: nounwind readnone 64 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #0 65 66 ; Function Attrs: nounwind readnone 67 declare i32 @llvm.hexagon.A2.sat(i64) #0 68 69 ; Function Attrs: nounwind readnone 70 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #0 71 72 ; Function Attrs: nounwind readnone 73 declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #0 74 75 ; Function Attrs: nounwind readnone 76 declare i32 @llvm.hexagon.A2.subsat(i32, i32) #0 77 78 ; Function Attrs: noreturn nounwind 79 declare void @llvm.trap() #2 80 81 attributes #0 = { nounwind readnone } 82 attributes #1 = { nounwind "target-cpu"="hexagonv55" } 83 attributes #2 = { noreturn nounwind } 84 85 !0 = !{!1, !1, i64 0} 86 !1 = !{!"short", !2, i64 0} 87 !2 = !{!"omnipotent char", !3, i64 0} 88 !3 = !{!"Simple C/C++ TBAA"} 89 !4 = !{!5, !5, i64 0} 90 !5 = !{!"long", !2, i64 0} 91
