1 ; RUN: llc -march=hexagon -enable-pipeliner -hexagon-expand-condsets=0 < %s 2 ; REQUIRES: asserts 3 4 ; Disable expand-condsets because it will assert on undefined registers. 5 6 ; Another test that the pipeliner doesn't ICE when reusing a 7 ; PHI in the epilog code. 8 9 @g0 = external global [18 x i16], align 8 10 11 ; Function Attrs: nounwind readnone 12 declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #0 13 14 ; Function Attrs: nounwind readnone 15 declare i32 @llvm.hexagon.A2.sxth(i32) #0 16 17 ; Function Attrs: nounwind 18 define void @f0() #1 { 19 b0: 20 %v0 = alloca [166 x i32], align 8 21 br label %b1 22 23 b1: ; preds = %b1, %b0 24 %v1 = icmp eq i16 undef, 0 25 br i1 %v1, label %b2, label %b1 26 27 b2: ; preds = %b1 28 br i1 undef, label %b3, label %b4 29 30 b3: ; preds = %b3, %b2 31 %v2 = add i32 0, 2 32 br i1 undef, label %b3, label %b4 33 34 b4: ; preds = %b3, %b2 35 %v3 = phi i32* [ undef, %b2 ], [ undef, %b3 ] 36 %v4 = phi i32 [ 0, %b2 ], [ %v2, %b3 ] 37 %v5 = getelementptr [18 x i16], [18 x i16]* @g0, i32 0, i32 undef 38 br label %b5 39 40 b5: ; preds = %b5, %b4 41 %v6 = phi i16 [ 0, %b4 ], [ %v17, %b5 ] 42 %v7 = phi i16 [ undef, %b4 ], [ %v6, %b5 ] 43 %v8 = phi i32 [ %v4, %b4 ], [ %v35, %b5 ] 44 %v9 = phi i32* [ %v3, %b4 ], [ undef, %b5 ] 45 %v10 = phi i16* [ undef, %b4 ], [ %v12, %b5 ] 46 %v11 = add i32 %v8, 0 47 %v12 = getelementptr inbounds i16, i16* %v10, i32 1 48 %v13 = sext i16 %v7 to i32 49 %v14 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 0, i32 %v13, i32 undef) 50 %v15 = getelementptr inbounds i16, i16* %v10, i32 2 51 %v16 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v14, i32 undef, i32 undef) 52 %v17 = load i16, i16* %v15, align 2, !tbaa !0 53 %v18 = sext i16 %v17 to i32 54 %v19 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v16, i32 %v18, i32 undef) 55 %v20 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v19, i32 undef) 56 %v21 = getelementptr [166 x i32], [166 x i32]* %v0, i32 0, i32 %v11 57 %v22 = load i32, i32* %v21, align 4 58 %v23 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v22, i32 undef) 59 %v24 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v23, i32 15) 60 %v25 = call i32 @llvm.hexagon.A2.sat(i64 %v24) 61 %v26 = call i32 @llvm.hexagon.A2.subsat(i32 %v20, i32 %v25) 62 %v27 = load i16, i16* %v5, align 4 63 %v28 = sext i16 %v27 to i32 64 %v29 = call i32 @llvm.hexagon.A2.sxth(i32 %v28) 65 %v30 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 undef, i32 %v29) 66 %v31 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v30, i32 15) 67 %v32 = call i32 @llvm.hexagon.A2.sat(i64 %v31) 68 %v33 = call i32 @llvm.hexagon.A2.subsat(i32 %v26, i32 %v32) 69 %v34 = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v33, i32 undef) 70 store i32 %v34, i32* %v9, align 4, !tbaa !4 71 %v35 = add i32 %v8, 1 72 %v36 = icmp eq i32 %v35, 164 73 br i1 %v36, label %b6, label %b5 74 75 b6: ; preds = %b5 76 call void @llvm.trap() 77 unreachable 78 } 79 80 ; Function Attrs: nounwind readnone 81 declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #0 82 83 ; Function Attrs: nounwind readnone 84 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #0 85 86 ; Function Attrs: nounwind readnone 87 declare i32 @llvm.hexagon.A2.sat(i64) #0 88 89 ; Function Attrs: nounwind readnone 90 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #0 91 92 ; Function Attrs: nounwind readnone 93 declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #0 94 95 ; Function Attrs: nounwind readnone 96 declare i32 @llvm.hexagon.A2.subsat(i32, i32) #0 97 98 ; Function Attrs: noreturn nounwind 99 declare void @llvm.trap() #2 100 101 attributes #0 = { nounwind readnone } 102 attributes #1 = { nounwind "target-cpu"="hexagonv55" } 103 attributes #2 = { noreturn nounwind } 104 105 !0 = !{!1, !1, i64 0} 106 !1 = !{!"short", !2, i64 0} 107 !2 = !{!"omnipotent char", !3, i64 0} 108 !3 = !{!"Simple C/C++ TBAA"} 109 !4 = !{!5, !5, i64 0} 110 !5 = !{!"long", !2, i64 0} 111
