1 ; RUN: llc -march=hexagon -verify-machineinstrs < %s 2 ; REQUIRES: asserts 3 4 ; Test that we constrain the new register operands for instructions 5 ; to be the same as the register class of the original instruction. 6 ; In this case, the register class of a valign scalar operand changed 7 ; from IntRegsLow8 to IntRegs, which is incorrect. 8 9 ; Function Attrs: nounwind 10 define void @f0() #0 { 11 b0: 12 br i1 undef, label %b1, label %b6 13 14 b1: ; preds = %b0 15 br label %b2 16 17 b2: ; preds = %b4, %b1 18 %v0 = phi <16 x i32> [ undef, %b1 ], [ %v17, %b4 ] 19 br label %b3 20 21 b3: ; preds = %b3, %b2 22 %v1 = phi i32 [ 0, %b2 ], [ %v19, %b3 ] 23 %v2 = phi i32 [ undef, %b2 ], [ %v18, %b3 ] 24 %v3 = phi <16 x i32> [ %v0, %b2 ], [ %v17, %b3 ] 25 %v4 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 0, i32 0) 26 %v5 = tail call <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32> undef, <16 x i32> undef, i32 %v2) 27 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffuh(<16 x i32> %v5, <16 x i32> undef) 28 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v6, <16 x i32> %v6) 29 %v8 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v7) 30 %v9 = tail call <16 x i32> @llvm.hexagon.V6.vlsrw(<16 x i32> %v8, i32 17) 31 %v10 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb(<16 x i32> %v9, i32 151587081) 32 %v11 = tail call <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32> %v10, <16 x i32> undef) 33 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32> undef, <16 x i32> %v11) 34 %v13 = tail call <16 x i32> @llvm.hexagon.V6.vmaxh(<16 x i32> %v12, <16 x i32> undef) 35 %v14 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh(<16 x i32> %v13, i32 %v4) 36 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh(<16 x i32> undef, i32 %v4) 37 %v16 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v14, <16 x i32> %v15) 38 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v3, <16 x i32> %v16) 39 %v18 = add nsw i32 %v2, -2 40 %v19 = add nsw i32 %v1, 1 41 %v20 = icmp eq i32 %v19, 2 42 br i1 %v20, label %b4, label %b3 43 44 b4: ; preds = %b3 45 br i1 undef, label %b5, label %b2 46 47 b5: ; preds = %b4 48 unreachable 49 50 b6: ; preds = %b0 51 ret void 52 } 53 54 ; Function Attrs: nounwind readnone 55 declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #1 56 57 ; Function Attrs: nounwind readnone 58 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 59 60 ; Function Attrs: nounwind readnone 61 declare <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32>, <16 x i32>, i32) #1 62 63 ; Function Attrs: nounwind readnone 64 declare <16 x i32> @llvm.hexagon.V6.vabsdiffuh(<16 x i32>, <16 x i32>) #1 65 66 ; Function Attrs: nounwind readnone 67 declare <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32>, <16 x i32>) #1 68 69 ; Function Attrs: nounwind readnone 70 declare <16 x i32> @llvm.hexagon.V6.vlsrw(<16 x i32>, i32) #1 71 72 ; Function Attrs: nounwind readnone 73 declare <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32>, <16 x i32>) #1 74 75 ; Function Attrs: nounwind readnone 76 declare <16 x i32> @llvm.hexagon.V6.vmpyiwb(<16 x i32>, i32) #1 77 78 ; Function Attrs: nounwind readnone 79 declare <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32>, <16 x i32>) #1 80 81 ; Function Attrs: nounwind readnone 82 declare <16 x i32> @llvm.hexagon.V6.vmaxh(<16 x i32>, <16 x i32>) #1 83 84 ; Function Attrs: nounwind readnone 85 declare <16 x i32> @llvm.hexagon.V6.vmpyiwh(<16 x i32>, i32) #1 86 87 ; Function Attrs: nounwind readnone 88 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 89 90 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 91 attributes #1 = { nounwind readnone } 92
