1 ; RUN: llc -march=hexagon -O3 < %s | FileCheck %s 2 3 ; Test that the MinStart computation, which is based upon the length 4 ; of the chain edges, is computed correctly. A bug in the code allowed 5 ; two instuctions that have a chain edge to be scheduled more than II 6 ; instructions apart. In this test, if two stores appear before the 7 ; store, then that is a bug. 8 9 ; CHECK: r{{[0-9]+}} = memw([[REG0:r([0-9]+)]]+#12) 10 ; CHECK-NOT: r{{[0-9]+}} = memw([[REG0]]+#12) 11 ; CHECK: memw([[REG0]]+#12) = r{{[0-9]+}} 12 13 %s.0 = type { i64, i32, i32, i32, i8* } 14 15 @g0 = external global %s.0, align 8 16 17 ; Function Attrs: nounwind 18 define void @f0() #0 { 19 b0: 20 %v0 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 8 21 %v1 = ashr i32 %v0, 3 22 br i1 undef, label %b1, label %b2 23 24 b1: ; preds = %b1, %b0 25 %v2 = phi i32 [ %v5, %b1 ], [ 0, %b0 ] 26 %v3 = load i8*, i8** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 4), align 4 27 %v4 = getelementptr inbounds i8, i8* %v3, i32 -1 28 store i8* %v4, i8** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 4), align 4 29 store i8 0, i8* %v4, align 1 30 %v5 = add nsw i32 %v2, 1 31 %v6 = icmp eq i32 %v5, %v1 32 br i1 %v6, label %b2, label %b1 33 34 b2: ; preds = %b1, %b0 35 ret void 36 } 37 38 attributes #0 = { nounwind "target-cpu"="hexagonv60" } 39
