1 ; RUN: llc -march=hexagon -enable-pipeliner < %s | FileCheck %s 2 3 ; Test that a store and load, that alias, are not put in the same packet. The 4 ; pipeliner altered the size of the memrefs for these instructions, which 5 ; resulted in no order dependence between the instructions in the DAG. No order 6 ; dependence was added since the size was set to UINT_MAX, but there is a 7 ; computation using the size that overflowed. 8 9 ; CHECK: endloop0 10 ; CHECK: memh([[REG:r([0-9]+)]]+#0) = 11 ; CHECK: = memh([[REG]]++#2) 12 13 ; Function Attrs: nounwind 14 define signext i16 @f0(i16* nocapture readonly %a0, i16* nocapture readonly %a1) local_unnamed_addr #0 { 15 b0: 16 %v0 = alloca [40 x i16], align 8 17 %v1 = bitcast [40 x i16]* %v0 to i8* 18 call void @llvm.lifetime.start.p0i8(i64 80, i8* nonnull %v1) #2 19 %v2 = getelementptr inbounds [40 x i16], [40 x i16]* %v0, i32 0, i32 0 20 br label %b1 21 22 b1: ; preds = %b1, %b0 23 %v3 = phi i16* [ %a1, %b0 ], [ %v24, %b1 ] 24 %v4 = phi i16* [ %v2, %b0 ], [ %v25, %b1 ] 25 %v5 = phi i32 [ 0, %b0 ], [ %v14, %b1 ] 26 %v6 = phi i32 [ 1, %b0 ], [ %v22, %b1 ] 27 %v7 = phi i32 [ 0, %b0 ], [ %v23, %b1 ] 28 %v8 = load i16, i16* %v3, align 2 29 %v9 = sext i16 %v8 to i32 30 %v10 = tail call i32 @llvm.hexagon.A2.aslh(i32 %v9) 31 %v11 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v10, i32 1) 32 %v12 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v11) 33 %v13 = trunc i32 %v12 to i16 34 store i16 %v13, i16* %v4, align 2 35 %v14 = add nuw nsw i32 %v5, 1 36 %v15 = icmp eq i32 %v14, 40 37 %v16 = getelementptr inbounds i16, i16* %a0, i32 %v7 38 %v17 = load i16, i16* %v16, align 2 39 %v18 = sext i16 %v17 to i32 40 %v19 = getelementptr inbounds [40 x i16], [40 x i16]* %v0, i32 0, i32 %v7 41 %v20 = load i16, i16* %v19, align 2 42 %v21 = sext i16 %v20 to i32 43 %v22 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v6, i32 %v18, i32 %v21) 44 %v23 = add nuw nsw i32 %v7, 1 45 %v24 = getelementptr i16, i16* %v3, i32 1 46 %v25 = getelementptr i16, i16* %v4, i32 1 47 br i1 %v15, label %b2, label %b1 48 49 b2: ; preds = %b1 50 %v26 = tail call signext i16 @f1(i32 %v22) #0 51 %v27 = sext i16 %v26 to i32 52 %v28 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v22, i32 %v27) 53 %v29 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v28) 54 %v30 = shl i32 %v29, 16 55 %v31 = ashr exact i32 %v30, 16 56 %v32 = icmp slt i32 %v30, 65536 57 br label %b3 58 59 b3: ; preds = %b2 60 call void @llvm.lifetime.end.p0i8(i64 80, i8* nonnull %v1) #2 61 ret i16 0 62 } 63 64 ; Function Attrs: argmemonly nounwind 65 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 66 67 ; Function Attrs: nounwind readnone 68 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2 69 70 ; Function Attrs: nounwind readnone 71 declare i32 @llvm.hexagon.A2.aslh(i32) #2 72 73 ; Function Attrs: nounwind readnone 74 declare i32 @llvm.hexagon.A2.asrh(i32) #2 75 76 ; Function Attrs: nounwind readnone 77 declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #2 78 79 ; Function Attrs: nounwind 80 declare signext i16 @f1(i32) local_unnamed_addr #0 81 82 ; Function Attrs: nounwind readnone 83 declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #2 84 85 ; Function Attrs: argmemonly nounwind 86 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 87 88 attributes #0 = { nounwind } 89 attributes #1 = { argmemonly nounwind } 90 attributes #2 = { nounwind readnone } 91
