1 ; RUN: llc -march=hexagon -enable-pipeliner < %s 2 ; REQUIRES: asserts 3 4 ; Test that we include all the nodes in the final node ordering 5 ; computation. This test creates two set of nodes that are processed 6 ; by computeNodeOrder(). 7 8 ; Function Attrs: nounwind 9 define void @f0(i32 %a0) #0 { 10 b0: 11 %v0 = add nsw i32 undef, 4 12 %v1 = ashr i32 %a0, 1 13 br label %b1 14 15 b1: ; preds = %b1, %b0 16 %v2 = phi i64 [ %v5, %b1 ], [ 0, %b0 ] 17 %v3 = phi i64 [ %v9, %b1 ], [ undef, %b0 ] 18 %v4 = phi i32 [ %v10, %b1 ], [ 0, %b0 ] 19 %v5 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v3, i64 undef) 20 %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 0, i32 0) 21 %v7 = tail call i64 @llvm.hexagon.S2.shuffeh(i64 %v6, i64 undef) 22 %v8 = trunc i64 %v7 to i32 23 %v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 undef) 24 %v10 = add nsw i32 %v4, 1 25 %v11 = icmp eq i32 %v10, %v1 26 br i1 %v11, label %b2, label %b1 27 28 b2: ; preds = %b1 29 %v12 = trunc i64 %v5 to i32 30 %v13 = inttoptr i32 %v0 to i32* 31 store i32 %v12, i32* %v13, align 4, !tbaa !0 32 call void @llvm.trap() 33 unreachable 34 } 35 36 ; Function Attrs: nounwind readnone 37 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 38 39 ; Function Attrs: nounwind readnone 40 declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1 41 42 ; Function Attrs: nounwind readnone 43 declare i64 @llvm.hexagon.S2.shuffeh(i64, i64) #1 44 45 ; Function Attrs: noreturn nounwind 46 declare void @llvm.trap() #2 47 48 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 49 attributes #1 = { nounwind readnone } 50 attributes #2 = { noreturn nounwind } 51 52 !0 = !{!1, !1, i64 0} 53 !1 = !{!"int", !2} 54 !2 = !{!"omnipotent char", !3} 55 !3 = !{!"Simple C/C++ TBAA"} 56
