1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 4 ; Test that we order instruction within a packet correctly. In this case, 5 ; we added a definition of a value after the use in a packet, which 6 ; caused an assert. 7 8 define void @f0(i32 %a0) { 9 b0: 10 %v0 = ashr i32 %a0, 1 11 br i1 undef, label %b3, label %b1 12 13 b1: ; preds = %b1, %b0 14 %v1 = phi i32 [ %v23, %b1 ], [ undef, %b0 ] 15 %v2 = phi i64 [ %v14, %b1 ], [ 0, %b0 ] 16 %v3 = phi i64 [ %v11, %b1 ], [ 0, %b0 ] 17 %v4 = phi i32 [ %v25, %b1 ], [ 0, %b0 ] 18 %v5 = phi i32 [ %v6, %b1 ], [ undef, %b0 ] 19 %v6 = phi i32 [ %v20, %b1 ], [ undef, %b0 ] 20 %v7 = phi i32 [ %v24, %b1 ], [ undef, %b0 ] 21 %v8 = tail call i32 @llvm.hexagon.A2.combine.lh(i32 %v6, i32 %v5) 22 %v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 undef) 23 %v10 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v1, i32 undef) 24 %v11 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v3, i64 %v9, i64 undef) 25 %v12 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5) 26 %v13 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v10, i64 undef, i32 2) 27 %v14 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v12, i64 %v13) 28 %v15 = inttoptr i32 %v7 to i16* 29 %v16 = load i16, i16* %v15, align 2 30 %v17 = sext i16 %v16 to i32 31 %v18 = add nsw i32 %v7, -8 32 %v19 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v12, i64 0) 33 %v20 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v17, i32 %v1) 34 %v21 = inttoptr i32 %v18 to i16* 35 %v22 = load i16, i16* %v21, align 2 36 %v23 = sext i16 %v22 to i32 37 %v24 = add nsw i32 %v7, -16 38 %v25 = add nsw i32 %v4, 1 39 %v26 = icmp eq i32 %v25, %v0 40 br i1 %v26, label %b2, label %b1 41 42 b2: ; preds = %b1 43 %v27 = phi i64 [ %v19, %b1 ] 44 %v28 = phi i64 [ %v14, %b1 ] 45 %v29 = phi i64 [ %v11, %b1 ] 46 %v30 = trunc i64 %v27 to i32 47 %v31 = trunc i64 %v28 to i32 48 %v32 = lshr i64 %v29, 32 49 %v33 = trunc i64 %v32 to i32 50 br label %b3 51 52 b3: ; preds = %b2, %b0 53 %v34 = phi i32 [ %v30, %b2 ], [ undef, %b0 ] 54 %v35 = phi i32 [ %v31, %b2 ], [ undef, %b0 ] 55 %v36 = phi i32 [ %v33, %b2 ], [ undef, %b0 ] 56 %v37 = bitcast i8* undef to i32* 57 store i32 %v35, i32* %v37, align 4 58 %v38 = getelementptr inbounds i8, i8* null, i32 8 59 %v39 = bitcast i8* %v38 to i32* 60 store i32 %v34, i32* %v39, align 4 61 %v40 = bitcast i8* undef to i32* 62 store i32 %v36, i32* %v40, align 4 63 call void @llvm.trap() 64 unreachable 65 } 66 67 ; Function Attrs: nounwind readnone 68 declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #0 69 70 ; Function Attrs: nounwind readnone 71 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #0 72 73 ; Function Attrs: nounwind readnone 74 declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #0 75 76 ; Function Attrs: nounwind readnone 77 declare i32 @llvm.hexagon.A2.combine.lh(i32, i32) #0 78 79 ; Function Attrs: nounwind readnone 80 declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #0 81 82 ; Function Attrs: noreturn nounwind 83 declare void @llvm.trap() #1 84 85 attributes #0 = { nounwind readnone } 86 attributes #1 = { noreturn nounwind } 87
