1 ; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s | FileCheck %s 2 3 ; Test that we generate the correct offsets after we removed unneeded 4 ; chain dependences between Phis and generated a better pipeline. 5 6 ; CHECK: loop0(.LBB0_[[LOOP:.]], 7 ; CHECK: .LBB0_[[LOOP]]: 8 ; CHECK: = memd([[REG0:(r[0-9]+)]]+#8) 9 ; CHECK: memd([[REG0]]++#8) = 10 ; CHECK: }{{[ \t]*}}:endloop0 11 12 @g0 = common global [400 x i8] zeroinitializer, align 8 13 @g1 = common global [400 x i8] zeroinitializer, align 8 14 15 ; Function Attrs: nounwind 16 define void @f0() #0 { 17 b0: 18 br label %b2 19 20 b1: ; preds = %b2 21 ret void 22 23 b2: ; preds = %b2, %b0 24 %v0 = phi i8* [ getelementptr inbounds ([400 x i8], [400 x i8]* @g0, i32 0, i32 0), %b0 ], [ %v23, %b2 ] 25 %v1 = phi i8* [ getelementptr inbounds ([400 x i8], [400 x i8]* @g1, i32 0, i32 0), %b0 ], [ %v24, %b2 ] 26 %v2 = phi i32 [ 0, %b0 ], [ %v21, %b2 ] 27 %v3 = bitcast i8* %v0 to <8 x i8>* 28 %v4 = load <8 x i8>, <8 x i8>* %v3, align 8 29 %v5 = bitcast i8* %v1 to <8 x i8>* 30 %v6 = load <8 x i8>, <8 x i8>* %v5, align 8 31 %v7 = bitcast <8 x i8> %v4 to <2 x i32> 32 %v8 = extractelement <2 x i32> %v7, i32 0 33 %v9 = extractelement <2 x i32> %v7, i32 1 34 %v10 = bitcast <8 x i8> %v6 to <2 x i32> 35 %v11 = extractelement <2 x i32> %v10, i32 0 36 %v12 = extractelement <2 x i32> %v10, i32 1 37 %v13 = tail call i64 @llvm.hexagon.S2.vzxtbh(i32 %v11) 38 %v14 = tail call i64 @llvm.hexagon.S2.vzxtbh(i32 %v12) 39 %v15 = tail call i64 @llvm.hexagon.M5.vmacbsu(i64 %v13, i32 %v8, i32 117901063) 40 %v16 = tail call i64 @llvm.hexagon.M5.vmacbsu(i64 %v14, i32 %v9, i32 117901063) 41 %v17 = tail call i32 @llvm.hexagon.S2.vtrunehb(i64 %v15) 42 %v18 = tail call i32 @llvm.hexagon.S2.vtrunehb(i64 %v16) 43 %v19 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v18, i32 %v17) 44 %v20 = bitcast i64 %v19 to <8 x i8> 45 store <8 x i8> %v20, <8 x i8>* %v5, align 8 46 %v21 = add nsw i32 %v2, 8 47 %v22 = icmp slt i32 %v2, 392 48 %v23 = getelementptr i8, i8* %v0, i32 8 49 %v24 = getelementptr i8, i8* %v1, i32 8 50 br i1 %v22, label %b2, label %b1 51 } 52 53 ; Function Attrs: nounwind readnone 54 declare i64 @llvm.hexagon.S2.vzxtbh(i32) #1 55 56 ; Function Attrs: nounwind readnone 57 declare i64 @llvm.hexagon.M5.vmacbsu(i64, i32, i32) #1 58 59 ; Function Attrs: nounwind readnone 60 declare i32 @llvm.hexagon.S2.vtrunehb(i64) #1 61 62 ; Function Attrs: nounwind readnone 63 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 64 65 attributes #0 = { nounwind } 66 attributes #1 = { nounwind readnone } 67
