1 ; RUN: llc -march=hexagon -enable-pipeliner -enable-bsb-sched=0 -join-liveintervals=false < %s | FileCheck %s 2 3 ; XFAIL: * 4 ; This test is failing after post-ra machine sinking. 5 6 ; Test that we generate the correct Phi values when there is a Phi that 7 ; references another Phi. We need to examine the other Phi to get the 8 ; correct value. We need to do this even if we haven't generated the 9 ; kernel code for the other Phi yet. 10 11 ; CHECK: v[[REG0:[0-9]+]] = v[[REG1:[0-9]+]] 12 ; CHECK: loop0 13 ; Check for copy REG0 = REG1 (via vcombine): 14 ; CHECK: v{{[0-9]+}}:[[REG0]] = vcombine(v{{[0-9]+}},v[[REG1]]) 15 ; CHECK: endloop0 16 17 ; Function Attrs: nounwind 18 define void @f0() #0 { 19 b0: 20 br i1 undef, label %b1, label %b2 21 22 b1: ; preds = %b1, %b0 23 %v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ] 24 %v1 = phi <16 x i32> [ %v4, %b1 ], [ undef, %b0 ] 25 %v2 = phi <16 x i32> [ %v1, %b1 ], [ undef, %b0 ] 26 %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v1, <16 x i32> %v2, i32 62) 27 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> undef) 28 %v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v1, i32 2) 29 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %v3, <16 x i32> %v5) 30 store <16 x i32> %v6, <16 x i32>* null, align 64 31 %v7 = add nsw i32 %v0, 1 32 %v8 = icmp slt i32 %v7, undef 33 br i1 %v8, label %b1, label %b2 34 35 b2: ; preds = %b1, %b0 36 ret void 37 } 38 39 ; Function Attrs: nounwind readnone 40 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 41 42 ; Function Attrs: nounwind readnone 43 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 44 45 ; Function Attrs: nounwind readnone 46 declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1 47 48 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 49 attributes #1 = { nounwind readnone } 50
