1 ; RUN: llc -march=hexagon -enable-pipeliner < %s 2 ; REQUIRES: asserts 3 4 ; Make sure pipeliner handle physical registers (e.g., used in 5 ; inline asm 6 7 @g0 = external global i32*, align 4 8 9 ; Function Attrs: nounwind 10 define i32 @f0(i32 %a0, i8** nocapture %a1) #0 { 11 b0: 12 br i1 undef, label %b1, label %b2 13 14 b1: ; preds = %b0 15 unreachable 16 17 b2: ; preds = %b0 18 br label %b3 19 20 b3: ; preds = %b3, %b2 21 br i1 undef, label %b4, label %b3 22 23 b4: ; preds = %b3 24 br label %b5 25 26 b5: ; preds = %b5, %b4 27 %v0 = phi i32* [ inttoptr (i32 33554432 to i32*), %b4 ], [ %v4, %b5 ] 28 %v1 = phi i32 [ 0, %b4 ], [ %v5, %b5 ] 29 %v2 = ptrtoint i32* %v0 to i32 30 tail call void asm sideeffect " r1 = $1\0A r0 = $0\0A memw(r0) = r1\0A dcfetch(r0)\0A", "r,r,~{r0},~{r1}"(i32 %v2, i32 %v1) #0 31 %v3 = load i32*, i32** @g0, align 4 32 %v4 = getelementptr inbounds i32, i32* %v3, i32 1 33 store i32* %v4, i32** @g0, align 4 34 %v5 = add nsw i32 %v1, 1 35 %v6 = icmp eq i32 %v5, 200 36 br i1 %v6, label %b6, label %b5 37 38 b6: ; preds = %b5 39 br label %b7 40 41 b7: ; preds = %b7, %b6 42 br i1 undef, label %b8, label %b7 43 44 b8: ; preds = %b7 45 ret i32 0 46 } 47 48 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 49
