1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s 2 ; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s | FileCheck %s --check-prefix=CHECKV60 3 4 ; Simple vector total. 5 ; CHECK: loop0(.LBB0_[[LOOP:.]], 6 ; CHECK: .LBB0_[[LOOP]]: 7 ; CHECK: add(r{{[0-9]+}},r{{[0-9]+}}) 8 ; CHECK-NEXT: memw(r{{[0-9]+}}++#4) 9 ; CHECK-NEXT: endloop0 10 11 ; V60 does not pipeline due to latencies. 12 ; CHECKV60: memw(r{{[0-9]+}}++#4) 13 ; CHECKV60: add(r{{[0-9]+}},r{{[0-9]+}}) 14 15 define i32 @f0(i32* %a0, i32 %a1) { 16 b0: 17 br label %b1 18 19 b1: ; preds = %b1, %b0 20 %v0 = phi i32 [ 0, %b0 ], [ %v4, %b1 ] 21 %v1 = phi i32* [ %a0, %b0 ], [ %v7, %b1 ] 22 %v2 = phi i32 [ 0, %b0 ], [ %v5, %b1 ] 23 %v3 = load i32, i32* %v1, align 4 24 %v4 = add nsw i32 %v3, %v0 25 %v5 = add nsw i32 %v2, 1 26 %v6 = icmp eq i32 %v5, 10000 27 %v7 = getelementptr i32, i32* %v1, i32 1 28 br i1 %v6, label %b2, label %b1 29 30 b2: ; preds = %b1 31 ret i32 %v4 32 } 33
