1 ; RUN: llc -march=hexagon -enable-aa-sched-mi < %s | FileCheck %s 2 3 ; The two memory addresses in the load and the memop below are trivially 4 ; non-aliasing. However, there are some cases where the scheduler cannot 5 ; determine this - in this case, it is because of the use of memops, that on the 6 ; surface. do not have only one mem operand. However, the backend knows MIs and 7 ; can step in and help some cases. In our case, if the base registers are the 8 ; same and the offsets different and the memory access size is such that 9 ; the two accesses won't overlap, we can tell the scheduler that there is no 10 ; dependence due to aliasing between the two instructions. 11 ; In the example below, this allows the load to be packetized with the memop. 12 ; CHECK: { 13 ; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*}}+#4) 14 ; CHECK-NEXT: memw(r{{[0-9]*}}+#0) += #3 15 ; CHECK: } 16 17 @g0 = common global [10 x i32] zeroinitializer, align 8 18 19 ; Function Attrs: nounwind 20 define void @f0(i32* nocapture %a0) #0 { 21 b0: 22 %v0 = load i32, i32* %a0, align 4, !tbaa !0 23 %v1 = add nsw i32 %v0, 3 24 store i32 %v1, i32* %a0, align 4, !tbaa !0 25 %v2 = getelementptr inbounds i32, i32* %a0, i32 1 26 %v3 = load i32, i32* %v2, align 4, !tbaa !0 27 store i32 %v3, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @g0, i32 0, i32 0), align 8, !tbaa !0 28 ret void 29 } 30 31 attributes #0 = { nounwind "target-cpu"="hexagonv60" } 32 33 !0 = !{!1, !1, i64 0} 34 !1 = !{!"int", !2} 35 !2 = !{!"omnipotent char", !3} 36 !3 = !{!"Simple C/C++ TBAA"} 37
