1 ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s 2 ; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}}) 3 4 target triple = "hexagon" 5 6 ; Function Attrs: nounwind 7 define void @f0(i32 %a0, <16 x i32> %a1) #0 { 8 b0: 9 %v0 = alloca i32, align 4 10 %v1 = alloca <16 x i32>, align 64 11 %v2 = alloca <16 x i32>, align 64 12 store i32 %a0, i32* %v0, align 4 13 store <16 x i32> %a1, <16 x i32>* %v1, align 64 14 %v3 = load i32, i32* %v0, align 4 15 %v4 = load <16 x i32>, <16 x i32>* %v2, align 64 16 call void asm sideeffect " $1 = vsetq($0);\0A", "r,q"(i32 %v3, <16 x i32> %v4) #1, !srcloc !0 17 ret void 18 } 19 20 ; Function Attrs: nounwind 21 define i32 @f1() #0 { 22 b0: 23 ret i32 0 24 } 25 26 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 27 attributes #1 = { nounwind } 28 29 !0 = !{i32 222} 30
