1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2 3 ; CHECK: vmem(r{{[0-9]+}}++#1) 4 ; CHECK: vmem(r{{[0-9]+}}++#1) 5 ; CHECK: vmem(r{{[0-9]+}}++#1) 6 ; CHECK: vmem(r{{[0-9]+}}++#1) 7 8 target triple = "hexagon" 9 10 ; Function Attrs: nounwind 11 define void @f0(i16* nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8* nocapture %a4, i32 %a5) #0 { 12 b0: 13 %v0 = ashr i32 %a3, 2 14 %v1 = ashr i32 %a3, 1 15 %v2 = add i32 %v1, %v0 16 %v3 = icmp sgt i32 %a2, 0 17 br i1 %v3, label %b1, label %b8 18 19 b1: ; preds = %b0 20 %v4 = sdiv i32 %a1, 64 21 %v5 = icmp sgt i32 %a1, 63 22 br label %b2 23 24 b2: ; preds = %b6, %b1 25 %v6 = phi i32 [ 0, %b1 ], [ %v56, %b6 ] 26 %v7 = ashr exact i32 %v6, 1 27 %v8 = mul nsw i32 %v7, %a3 28 br i1 %v5, label %b3, label %b6 29 30 b3: ; preds = %b2 31 %v9 = add nsw i32 %v6, 1 32 %v10 = mul nsw i32 %v9, %a5 33 %v11 = mul nsw i32 %v6, %a5 34 %v12 = add i32 %v2, %v8 35 %v13 = add i32 %v8, %v0 36 %v14 = add i32 %v8, %v1 37 %v15 = getelementptr inbounds i8, i8* %a4, i32 %v10 38 %v16 = getelementptr inbounds i8, i8* %a4, i32 %v11 39 %v17 = getelementptr inbounds i16, i16* %a0, i32 %v12 40 %v18 = getelementptr inbounds i16, i16* %a0, i32 %v13 41 %v19 = getelementptr inbounds i16, i16* %a0, i32 %v14 42 %v20 = getelementptr inbounds i16, i16* %a0, i32 %v8 43 %v21 = bitcast i8* %v15 to <16 x i32>* 44 %v22 = bitcast i8* %v16 to <16 x i32>* 45 %v23 = bitcast i16* %v17 to <16 x i32>* 46 %v24 = bitcast i16* %v18 to <16 x i32>* 47 %v25 = bitcast i16* %v19 to <16 x i32>* 48 %v26 = bitcast i16* %v20 to <16 x i32>* 49 br label %b4 50 51 b4: ; preds = %b4, %b3 52 %v27 = phi i32 [ 0, %b3 ], [ %v54, %b4 ] 53 %v28 = phi <16 x i32>* [ %v26, %b3 ], [ %v34, %b4 ] 54 %v29 = phi <16 x i32>* [ %v25, %b3 ], [ %v36, %b4 ] 55 %v30 = phi <16 x i32>* [ %v24, %b3 ], [ %v38, %b4 ] 56 %v31 = phi <16 x i32>* [ %v23, %b3 ], [ %v40, %b4 ] 57 %v32 = phi <16 x i32>* [ %v21, %b3 ], [ %v53, %b4 ] 58 %v33 = phi <16 x i32>* [ %v22, %b3 ], [ %v52, %b4 ] 59 %v34 = getelementptr inbounds <16 x i32>, <16 x i32>* %v28, i32 1 60 %v35 = load <16 x i32>, <16 x i32>* %v28, align 64, !tbaa !0 61 %v36 = getelementptr inbounds <16 x i32>, <16 x i32>* %v29, i32 1 62 %v37 = load <16 x i32>, <16 x i32>* %v29, align 64, !tbaa !0 63 %v38 = getelementptr inbounds <16 x i32>, <16 x i32>* %v30, i32 1 64 %v39 = load <16 x i32>, <16 x i32>* %v30, align 64, !tbaa !0 65 %v40 = getelementptr inbounds <16 x i32>, <16 x i32>* %v31, i32 1 66 %v41 = load <16 x i32>, <16 x i32>* %v31, align 64, !tbaa !0 67 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v35, <16 x i32> %v37) 68 %v43 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v35, <16 x i32> %v37) 69 %v44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v41) 70 %v45 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v39, <16 x i32> %v41) 71 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v42, <16 x i32> %v44) 72 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v42, <16 x i32> %v44) 73 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v43, <16 x i32> %v45) 74 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v43, <16 x i32> %v45) 75 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v47, <16 x i32> %v46) 76 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v49, <16 x i32> %v48) 77 %v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v33, i32 1 78 store <16 x i32> %v50, <16 x i32>* %v33, align 64, !tbaa !0 79 %v53 = getelementptr inbounds <16 x i32>, <16 x i32>* %v32, i32 1 80 store <16 x i32> %v51, <16 x i32>* %v32, align 64, !tbaa !0 81 %v54 = add nsw i32 %v27, 1 82 %v55 = icmp slt i32 %v54, %v4 83 br i1 %v55, label %b4, label %b5 84 85 b5: ; preds = %b4 86 br label %b6 87 88 b6: ; preds = %b5, %b2 89 %v56 = add nsw i32 %v6, 2 90 %v57 = icmp slt i32 %v56, %a2 91 br i1 %v57, label %b2, label %b7 92 93 b7: ; preds = %b6 94 br label %b8 95 96 b8: ; preds = %b7, %b0 97 ret void 98 } 99 100 ; Function Attrs: nounwind readnone 101 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 102 103 ; Function Attrs: nounwind readnone 104 declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1 105 106 ; Function Attrs: nounwind readnone 107 declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #1 108 109 ; Function Attrs: nounwind readnone 110 declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #1 111 112 ; Function Attrs: nounwind readnone 113 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 114 115 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 116 attributes #1 = { nounwind readnone } 117 118 !0 = !{!1, !1, i64 0} 119 !1 = !{!"omnipotent char", !2, i64 0} 120 !2 = !{!"Simple C/C++ TBAA"} 121
