1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2 ; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}}) 3 ; CHECK: .comm g0,256,256 4 ; CHECK: .comm g1,128,128 5 6 target triple = "hexagon" 7 8 @g0 = common global <64 x i32> zeroinitializer, align 256 9 @g1 = common global <32 x i32> zeroinitializer, align 128 10 11 ; Function Attrs: nounwind 12 define i32 @f0() #0 { 13 b0: 14 %v0 = alloca i32, align 4 15 store i32 0, i32* %v0 16 %v1 = call i32 @f1(i8 zeroext 0) 17 call void bitcast (void (...)* @f2 to void ()*)() 18 %v2 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1) 19 %v3 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 2) 20 %v4 = call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v2, <32 x i32> %v3) 21 %v5 = call <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32> %v4, i32 12) 22 store <64 x i32> %v5, <64 x i32>* @g0, align 256 23 call void @f3(i32 2048, i8* bitcast (<64 x i32>* @g0 to i8*)) 24 ret i32 0 25 } 26 27 declare i32 @f1(i8 zeroext) #0 28 29 declare void @f2(...) #0 30 31 ; Function Attrs: nounwind readnone 32 declare <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32>, i32) #1 33 34 ; Function Attrs: nounwind readnone 35 declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #1 36 37 ; Function Attrs: nounwind readnone 38 declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1 39 40 declare void @f3(i32, i8*) #0 41 42 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } 43 attributes #1 = { nounwind readnone } 44
