1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; CHECK: if (p{{[0-3]}}) v{{[0-9]+}} = v{{[0-9]+}} 4 5 target triple = "hexagon" 6 7 ; Function Attrs: nounwind 8 define void @fast9_detect_coarse(i8* nocapture readnone %img, i32 %xsize, i32 %stride, i32 %barrier, i32* nocapture %bitmask, i32 %boundary) #0 { 9 entry: 10 %0 = bitcast i32* %bitmask to <16 x i32>* 11 %1 = mul i32 %boundary, -2 12 %sub = add i32 %1, %xsize 13 %rem = and i32 %boundary, 63 14 %add = add i32 %sub, %rem 15 %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1) 16 %3 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 17 %4 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %add) 18 %5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %3, <512 x i1> %4, i32 12) 19 %and4 = and i32 %add, 511 20 %cmp = icmp eq i32 %and4, 0 21 %sMaskR.0 = select i1 %cmp, <16 x i32> %2, <16 x i32> %5 22 %cmp547 = icmp sgt i32 %add, 0 23 br i1 %cmp547, label %for.body.lr.ph, label %for.end 24 25 for.body.lr.ph: ; preds = %entry 26 %6 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %boundary) 27 %7 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1> %6, i32 16843009) 28 %8 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %7) 29 %9 = add i32 %rem, %xsize 30 %10 = add i32 %9, -1 31 %11 = add i32 %10, %1 32 %12 = lshr i32 %11, 9 33 %13 = mul i32 %12, 16 34 %14 = add nuw nsw i32 %13, 16 35 %scevgep = getelementptr i32, i32* %bitmask, i32 %14 36 br label %for.body 37 38 for.body: ; preds = %for.body.lr.ph, %for.body 39 %i.050 = phi i32 [ %add, %for.body.lr.ph ], [ %sub6, %for.body ] 40 %sMask.049 = phi <16 x i32> [ %8, %for.body.lr.ph ], [ %2, %for.body ] 41 %optr.048 = phi <16 x i32>* [ %0, %for.body.lr.ph ], [ %incdec.ptr, %for.body ] 42 %15 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %sMask.049) 43 %incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %optr.048, i32 1 44 store <16 x i32> %15, <16 x i32>* %optr.048, align 64 45 %sub6 = add nsw i32 %i.050, -512 46 %cmp5 = icmp sgt i32 %sub6, 0 47 br i1 %cmp5, label %for.body, label %for.cond.for.end_crit_edge 48 49 for.cond.for.end_crit_edge: ; preds = %for.body 50 %scevgep51 = bitcast i32* %scevgep to <16 x i32>* 51 br label %for.end 52 53 for.end: ; preds = %for.cond.for.end_crit_edge, %entry 54 %optr.0.lcssa = phi <16 x i32>* [ %scevgep51, %for.cond.for.end_crit_edge ], [ %0, %entry ] 55 %16 = load <16 x i32>, <16 x i32>* %optr.0.lcssa, align 64 56 %17 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %16, <16 x i32> %sMaskR.0) 57 store <16 x i32> %17, <16 x i32>* %optr.0.lcssa, align 64 58 ret void 59 } 60 61 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 62 declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1 63 declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <512 x i1>, i32) #1 64 declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 65 declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1 66 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 67 68 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 69 attributes #1 = { nounwind readnone } 70
