1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 3 ; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vcombine(v{{[0-9]+}},v{{[0-9]+}}) 4 5 target triple = "hexagon" 6 7 ; Function Attrs: nounwind 8 define void @f0(i8* nocapture readnone %a0, i32 %a1, i32 %a2, i32 %a3, i32* nocapture %a4, i32 %a5) #0 { 9 b0: 10 %v0 = bitcast i32* %a4 to <16 x i32>* 11 %v1 = mul i32 %a5, -2 12 %v2 = add i32 %v1, %a1 13 %v3 = and i32 %a5, 63 14 %v4 = add i32 %v2, %v3 15 %v5 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1) 16 %v6 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 17 %v7 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v4) 18 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %v6, <512 x i1> %v7, i32 12) 19 %v9 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v8, <16 x i32> %v8) 20 %v10 = and i32 %v4, 511 21 %v11 = icmp eq i32 %v10, 0 22 br i1 %v11, label %b1, label %b2 23 24 b1: ; preds = %b0 25 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v5, <16 x i32> %v8) 26 br label %b2 27 28 b2: ; preds = %b1, %b0 29 %v13 = phi <32 x i32> [ %v12, %b1 ], [ %v9, %b0 ] 30 %v14 = icmp sgt i32 %v4, 0 31 br i1 %v14, label %b3, label %b6 32 33 b3: ; preds = %b2 34 %v15 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a5) 35 %v16 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1> %v15, i32 16843009) 36 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %v16) 37 %v18 = add i32 %v3, %a1 38 %v19 = add i32 %v18, -1 39 %v20 = add i32 %v19, %v1 40 %v21 = lshr i32 %v20, 9 41 %v22 = mul i32 %v21, 16 42 %v23 = add nuw nsw i32 %v22, 16 43 %v24 = getelementptr i32, i32* %a4, i32 %v23 44 br label %b4 45 46 b4: ; preds = %b4, %b3 47 %v25 = phi i32 [ %v4, %b3 ], [ %v30, %b4 ] 48 %v26 = phi <16 x i32> [ %v17, %b3 ], [ %v5, %b4 ] 49 %v27 = phi <16 x i32>* [ %v0, %b3 ], [ %v29, %b4 ] 50 %v28 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %v26) 51 %v29 = getelementptr inbounds <16 x i32>, <16 x i32>* %v27, i32 1 52 store <16 x i32> %v28, <16 x i32>* %v27, align 64, !tbaa !0 53 %v30 = add nsw i32 %v25, -512 54 %v31 = icmp sgt i32 %v30, 0 55 br i1 %v31, label %b4, label %b5 56 57 b5: ; preds = %b4 58 %v32 = bitcast i32* %v24 to <16 x i32>* 59 br label %b6 60 61 b6: ; preds = %b5, %b2 62 %v33 = phi <16 x i32>* [ %v32, %b5 ], [ %v0, %b2 ] 63 %v34 = load <16 x i32>, <16 x i32>* %v33, align 64, !tbaa !0 64 %v35 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13) 65 %v36 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v34, <16 x i32> %v35) 66 store <16 x i32> %v36, <16 x i32>* %v33, align 64, !tbaa !0 67 ret void 68 } 69 70 ; Function Attrs: nounwind readnone 71 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 72 73 ; Function Attrs: nounwind readnone 74 declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1 75 76 ; Function Attrs: nounwind readnone 77 declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <512 x i1>, i32) #1 78 79 ; Function Attrs: nounwind readnone 80 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 81 82 ; Function Attrs: nounwind readnone 83 declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 84 85 ; Function Attrs: nounwind readnone 86 declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1 87 88 ; Function Attrs: nounwind readnone 89 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 90 91 ; Function Attrs: nounwind readnone 92 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 93 94 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 95 attributes #1 = { nounwind readnone } 96 97 !0 = !{!1, !1, i64 0} 98 !1 = !{!"omnipotent char", !2, i64 0} 99 !2 = !{!"Simple C/C++ TBAA"} 100
