1 ; RUN: llc -march=hexagon -O2 -disable-block-placement < %s | FileCheck %s 2 ; Disable block placement because it intereferes with the generated code. 3 4 ; CHECK: if (p{{[0-9]*}}) jump:nt .LBB0_2 5 ; CHECK-NEXT: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0) 6 ; CHECK-NEXT: } 7 8 target triple = "hexagon" 9 10 @g0 = global <16 x i32> zeroinitializer, align 64 11 12 ; Function Attrs: nounwind 13 define void @f0(i16* nocapture readonly %a0, i32 %a1, i32 %a2, i16* nocapture %a3) #0 { 14 b0: 15 %v0 = mul i32 %a2, -2 16 %v1 = add i32 %v0, 64 17 %v2 = bitcast i16* %a3 to <16 x i32>* 18 %v3 = load <16 x i32>, <16 x i32>* @g0, align 64 19 %v4 = sdiv i32 %a1, 32 20 %v5 = icmp sgt i32 %a1, 31 21 br i1 %v5, label %b1, label %b4 22 23 b1: ; preds = %b0 24 %v6 = bitcast i16* %a0 to <16 x i32>* 25 %v7 = icmp sgt i32 %a1, 63 26 %v8 = mul i32 %v4, 32 27 %v9 = select i1 %v7, i32 %v8, i32 32 28 %v10 = getelementptr i16, i16* %a3, i32 %v9 29 br label %b2 30 31 b2: ; preds = %b2, %b1 32 %v11 = phi i32 [ 0, %b1 ], [ %v19, %b2 ] 33 %v12 = phi <16 x i32> [ %v3, %b1 ], [ %v16, %b2 ] 34 %v13 = phi <16 x i32>* [ %v2, %b1 ], [ %v18, %b2 ] 35 %v14 = phi <16 x i32>* [ %v6, %b1 ], [ %v15, %b2 ] 36 %v15 = getelementptr inbounds <16 x i32>, <16 x i32>* %v14, i32 1 37 %v16 = load <16 x i32>, <16 x i32>* %v14, align 64 38 %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v16, <16 x i32> %v12, i32 %v1) 39 %v18 = getelementptr inbounds <16 x i32>, <16 x i32>* %v13, i32 1 40 store <16 x i32> %v17, <16 x i32>* %v13, align 64 41 %v19 = add nsw i32 %v11, 1 42 %v20 = icmp slt i32 %v19, %v4 43 br i1 %v20, label %b2, label %b3 44 45 b3: ; preds = %b2 46 %v21 = bitcast i16* %v10 to <16 x i32>* 47 %v22 = load <16 x i32>, <16 x i32>* @g0, align 64 48 br label %b4 49 50 b4: ; preds = %b3, %b0 51 %v23 = phi <16 x i32> [ %v22, %b3 ], [ %v3, %b0 ] 52 %v24 = phi <16 x i32> [ %v16, %b3 ], [ %v3, %b0 ] 53 %v25 = phi <16 x i32>* [ %v21, %b3 ], [ %v2, %b0 ] 54 %v26 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v23, <16 x i32> %v24, i32 %v1) 55 store <16 x i32> %v26, <16 x i32>* %v25, align 64 56 ret void 57 } 58 59 ; Function Attrs: nounwind readnone 60 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 61 62 attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length64b" } 63 attributes #1 = { nounwind readnone } 64
