1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 ; generate vmems for W_equals_W (vassignp) 3 ; CHECK: vmem 4 ; CHECK: vmem 5 ; CHECK: vmem 6 ; CHECK: vmem 7 8 target triple = "hexagon" 9 10 @g0 = common global [15 x <32 x i32>] zeroinitializer, align 64 11 @g1 = common global <32 x i32> zeroinitializer, align 64 12 13 ; Function Attrs: nounwind 14 define i32 @f0() #0 { 15 b0: 16 %v0 = alloca i32, align 4 17 %v1 = alloca i32, align 4 18 store i32 0, i32* %v0 19 store i32 0, i32* %v1, align 4 20 %v2 = load <32 x i32>, <32 x i32>* getelementptr inbounds ([15 x <32 x i32>], [15 x <32 x i32>]* @g0, i32 0, i32 0), align 64 21 %v3 = call <32 x i32> @llvm.hexagon.V6.vassignp(<32 x i32> %v2) 22 store <32 x i32> %v3, <32 x i32>* @g1, align 64 23 ret i32 0 24 } 25 26 ; Function Attrs: nounwind readnone 27 declare <32 x i32> @llvm.hexagon.V6.vassignp(<32 x i32>) #1 28 29 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 30 attributes #1 = { nounwind readnone } 31
